公开(公告)号：CA1236929A

公开(公告)日：1988-05-17

申请号：CA499662

申请日：1986-01-15

Applicant: IBM

Inventor： BEHA JOHANNES G ,  DREYFUS RUSSELL W ,  HARTSTEIN ALLAN M ,  RUBLOFF GARY W

IPC: G01R31/28 ,  G01R31/308 ,  H01L21/66 ,  G01R31/26

Abstract: PHOTON ASSISTED TUNNELING TESTING OF PASSIVATED INTEGRATED CIRCUITS Covering metal test pads of a passivated integrated circuit process intermediate wafer or completed integrated circuit chip-to-test, with a thin conductive overlayer, and then accessing the test pads through the passivation layer and conductive overlayer, by a pulsed laser to provide voltage-modulated photon-assisted tunneling through the insulation layer, to the conductive overlayer as an electron current, and detecting the resulting electron current, provides a nondestructive test of integrated circuits. The passivation, normally present to protect the integrated circuit, also lowers the threshold for photoelectron emission. The conductive overlayer acts as a photoelectron collector for the detector. A chip-to-test which is properly designed for photon assisted tunneling testing has test sites accessible to laser photons even though passivated. Such a chip-to-test may be nondestructively tested in air at one or several stages of its processing, without the sacrifices of mechanical probing or of bringing test sites out to output pads. The conductive overlayer may be removed after tests have been completed. Integrated circuit process intermediate chips may be specially designed for testability, with test sites grouped for easy access through windows left uncovered by subsequent layers.

公开(公告)号：HK1035243A1

公开(公告)日：2001-11-16

申请号：HK01105871

申请日：2001-08-21

Applicant: IBM

Inventor： PUZAK THOMAS R ,  HARTSTEIN ALLAN M ,  CHARNEY MARK ,  PRENER DANIEL A ,  ODEN PETER H

IPC: G06F20060101 ,  G06F9/38 ,  G06F9/42 ,  G06F

Abstract: A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.

公开(公告)号：CA1145022A

公开(公告)日：1983-04-19

申请号：CA339027

申请日：1979-11-02

Applicant: IBM

Inventor： HARTSTEIN ALLAN M ,  PETERSEN KURT E

IPC: H04N5/74 ,  G02B27/50 ,  G02F1/19 ,  G09F9/37 ,  H01H59/00 ,  G08B5/24

Abstract: MICROMECHANICAL DISPLAY LOGIC AND ARRAY A display device, addressing circuitry, and semiconductor control logic are all portions of an integrated structure formed by thin film technology on a single silicon wafer. The display comprises a thin film micromechanical electrostatic form of light reflective display formed by depositing thin films upon a silicon wafer and selectively etching to form metal-amorphous oxide micromechanical leaves deflected by applying potential thereto to provide electrostatic deflection. MOSFET devices are also formed upon the silicon wafer in juxtaposition with a plurality of micromechanical display elements. Addressing circuitry is connected to the MOSFET devices. SA978-003