公开(公告)号：JP2000244316A

公开(公告)日：2000-09-08

申请号：JP3939299

申请日：1999-02-18

Applicant: IBM

Inventor： YASUDA TAKAO ,  HATANI NAOHISA

IPC: H03M1/10 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To provide a differential input interface that does not require matching between a DC level in a system including a differential input and a DC level of a differential input signal and receives no effect of external offset, and to provide a method for adjusting the DC level of the differential input signal. SOLUTION: The differential input interface 10 is configured by using a reference level output means 40 that outputs the same DC level as that of a DC level Vref in an A/D converter 100, capacitors 50, 60 that cut off DC components in differential input signals IN(P), IN(N), and resistors 52, 62 that make a mean value of the non-inverted component and the inverted component of the differential input signal, whose DC component is cut off, match the output DC level Vref of the reference level output means 40.

公开(公告)号：JP2001044771A

公开(公告)日：2001-02-16

申请号：JP19738699

申请日：1999-07-12

Applicant: IBM

Inventor： HATANI NAOHISA

IPC: H03K5/08 ,  G01R19/165 ,  H03F3/34 ,  H03F3/45 ,  H03K5/24

Abstract: PROBLEM TO BE SOLVED: To provide an analog voltage comparator circuit (comparator) that can correct (cancel) an input voltage offset independently of a semiconductor process. SOLUTION: The voltage comparator circuit has a 1st comparator 1 and a 2nd comparator 2 that are operated inversely to each other, a 3rd comparator 3 that receives outputs from the two comparators 1, 2, a 1st switch S1 that is connected to an inverting input (-) of the 1st comparator 1 and a noninverting input (+) of the 2nd comparator 2 via a 1st capacitor C1 and selects an input voltage Vi or a reference voltage Vref to apply the selected voltage to the inverting input (-) of the 1st comparator 1 and the noninverting input (+) of the 2nd comparator 2, a 2nd capacitor C2 placed between the noniverting input (+) of the 1st comparator 1 and the inverting input (-) of the 2nd comparator 2, a 2nd switch S2 placed between the inverting input (-) of the 1st comparator 1 and an output 5, and a 3rd switch S3 placed between the inverting input (-) of the 2nd comparator 2 and an output 6.

公开(公告)号：JP2002026296A

公开(公告)日：2002-01-25

申请号：JP2000187459

申请日：2000-06-22

Applicant: IBM

Inventor： HATANI NAOHISA ,  OKUBO MANABU

IPC: H01L21/82 ,  H01L27/118

Abstract: PROBLEM TO BE SOLVED: To make easier the layout of first-layer wiring which connects the gate wiring of each device (MISFET) of diagonally arranged gate arrays to those of the other devices when interconnecting the gate wiring to each other. SOLUTION: Part of the connecting area 10 of gate wiring 4-21p is formed by extending the part to the space between the gate wiring 4-20p of a MISFET Qp20 adjoining to the MISFET Qp21 constituted of the wiring 4-21p and the gate wiring 4-20n of a MISFET Qn20. Since the part of the connecting area (contact section) 10 of the gate wiring is formed between the MISFETs adjoining to each other in the x-direction, the connection between the gate wiring of MISFETs adjoining to each other in the y-direction become easier.

公开(公告)号：JP2000151403A

公开(公告)日：2000-05-30

申请号：JP31317998

申请日：1998-11-04

Applicant: IBM

Inventor： HATANI NAOHISA ,  OKUBO MANABU

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/66 ,  H03M1/78

Abstract: PROBLEM TO BE SOLVED: To decrease the nonlinearity error of an analog output with respect to a digital input to the D/A converter without employing any special analog process. SOLUTION: The n-bit D/A converter 2 is provided with a correction signal generating means 4 that generates a digital correction signal in m-bit (m is a positive integer) with respect to a digital input signal D in n-bit (n is a positive integer being 2 or over) and with a D/A conversion means 6 that converts a digital signal in (n+m)-bit consisting of the n-bit input signal D and the m-bit correction signal into an analog signal.