公开(公告)号：JP2000244316A

公开(公告)日：2000-09-08

申请号：JP3939299

申请日：1999-02-18

Applicant: IBM

Inventor： YASUDA TAKAO ,  HATANI NAOHISA

IPC: H03M1/10 ,  H03F3/45 ,  H03M1/06 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To provide a differential input interface that does not require matching between a DC level in a system including a differential input and a DC level of a differential input signal and receives no effect of external offset, and to provide a method for adjusting the DC level of the differential input signal. SOLUTION: The differential input interface 10 is configured by using a reference level output means 40 that outputs the same DC level as that of a DC level Vref in an A/D converter 100, capacitors 50, 60 that cut off DC components in differential input signals IN(P), IN(N), and resistors 52, 62 that make a mean value of the non-inverted component and the inverted component of the differential input signal, whose DC component is cut off, match the output DC level Vref of the reference level output means 40.

公开(公告)号：JP2000124800A

公开(公告)日：2000-04-28

申请号：JP28755398

申请日：1998-10-09

Applicant: IBM

Inventor： YASUDA TAKAO

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/18

Abstract: PROBLEM TO BE SOLVED: To adjust the oscillation-frequency-to-control-voltage characteristics of a VCO(voltage controlled oscillator) so as to surely oscillate a target frequency within a control voltage range. SOLUTION: In this calibration method, by a step for adjusting the oscillation- frequency-to-control-voltage characteristics so as to turn an oscillation frequency at a reference voltage Vref within the range of a control voltage Vc to the maximum value ft-H of a requested target frequency (the state of a Q point) and a step for confirming that the voltage for turning the oscillation frequency to the minimum value ft-L of the target frequency is present (the state of an R point) within the range from the lower limit value Vclamp-L of the control voltage to the reference voltage Vref, the oscillation-frequency-to-control-voltage characteristics of the VCO are adjusted.

公开(公告)号：JP2010250892A

公开(公告)日：2010-11-04

申请号：JP2009098747

申请日：2009-04-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YASUDA TAKAO

IPC: G11C11/41 ,  G11C11/413

CPC classification number: G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device optimizing timing of activation of a sense amplifier. SOLUTION: An SRAM 10 includes: word lines WL; bit lines BL; address decoders 14 for selecting one of the word lines WL in response to an address signal AD; the sense amplifier 18 activated in response to a sense amplifier enable signal SAE; and a sense amplifier control circuit 22 for generating the sense amplifier enable signal SAE. In this device, the more distant the word line WL is from the sense amplifier 18, the longer the sense amplifier control circuit 22 sets the delay time of the sense amplifier enable signal SAE so that the more distant the word line WL is from the sense amplifier 18, the later the sense amplifier 18 is activated. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种优化读出放大器的激活定时的半导体存储器件。 解决方案：SRAM 10包括：字线WL; 位线BL; 地址解码器14，用于响应于地址信号AD选择字线WL之一; 读出放大器18响应于读出放大器使能信号SAE而被激活; 以及用于产生读出放大器使能信号SAE的读出放大器控制电路22。 在该装置中，字线WL距离读出放大器18越远，读出放大器控制电路22设定读出放大器使能信号SAE的延迟时间越长，使得字线WL越远离感测 放大器18，感测放大器18被激活。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2003046387A

公开(公告)日：2003-02-14

申请号：JP2001206736

申请日：2001-07-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： YASUDA TAKAO

IPC: H03L7/081 ,  H03L7/10

Abstract: PROBLEM TO BE SOLVED: To shorten time until a PLL circuit 10 of an unlock state becomes a lock state. SOLUTION: A variable delay device 25 is provided to a post-stage of a voltage-controlled oscillator 21, an output of the variable delay device 25 is used for an output of the PLL circuit 10, and fed to a phase frequency detector 16 as a feedback signal via a 1/N frequency divider 29 or the like. An up-down counter 39 generates a count value corresponding to a lead or lag amount of the feedback signal corresponding to a reference input clock signal. The variable delay device 25 delays each cycle of an oscillation signal of the voltage- controlled oscillator 21 by a delay time corresponding to a control delay control variable from the up-down counter 39 and provides an output. On the basis of that a phase of an output clock of the PLL circuit 10 for a lockup period is lagged from or led to a phase of the reference input clock, the delay is controlled and advancing or lagging only the phase momentarily can reduce the lockup period of the PLL circuit 10.

Abstract translation: 要解决的问题：缩短时间，直到解锁状态的PLL电路10变为锁定状态。 解决方案：将可变延迟装置25提供给压控振荡器21的后级，可变延迟装置25的输出用于PLL电路10的输出，并被馈送到相位频率检测器16，作为 通过1 / N分频器29等的反馈信号。 升降计数器39产生与对应于参考输入时钟信号的反馈信号的引导或滞后量对应的计数值。 可变延迟装置25将压控振荡器21的振荡信号的每个周期延迟与来自升降计数器39的控制延迟控制变量对应的延迟时间并提供输出。 基于该锁相周期的PLL电路10的输出时钟的相位滞后于或者被引导到参考输入时钟的相位，延迟被控制并且仅延迟或仅滞后相位可以减少锁定 PLL电路10的周期。

公开(公告)号：JPH11214990A

公开(公告)日：1999-08-06

申请号：JP955698

申请日：1998-01-21

Applicant: IBM

Inventor： YASUDA TAKAO

IPC: G11B5/012 ,  G11B20/14 ,  H03L7/081 ,  H03L7/091 ,  H03L7/10

Abstract: PROBLEM TO BE SOLVED: To provide a PLL circuit and a method for phase lock that are capable performing the phase lock of a sample clock with a target clock at an early stage. SOLUTION: This phase lock loop(PLL) circuit 200 includes a voltage- controlled oscillator 12, a differential correction circuit 10 for deciding the phase difference between an output signal of the voltage control oscillator 12 and a target signal, and a variable delay circuit 11 for instantly changing the initial delay of the output signal of the voltage control oscillator 12.

公开(公告)号：JP2005130302A

公开(公告)日：2005-05-19

申请号：JP2003365224

申请日：2003-10-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YASUDA TAKAO ,  SUNANAGA TOSHIO

IPC: H03K3/353 ,  G11C11/406 ,  H03K3/0231

CPC classification number: H03K3/0231

Abstract: PROBLEM TO BE SOLVED: To provide an oscillator used for semiconductor memories and capable of reducing power consumption.
SOLUTION: When the voltage V1 of a comparison node N1 becomes larger than a first reference voltage Vref1, a differential amplifier 101 inside the oscillator 1 makes a pulse generating circuit 110 output pulses. When the pulses are output, the comparison node N1 is discharged by a charging/discharging circuit 105. At this point, a control circuit 4 inactivates a first control signal CT1 and stops the differential amplifier 101. After the comparison node N1 is discharged, it is gradually charged by the charging/discharging circuit 105. As a result, when the voltage V1 exceeds a second reference voltage Vref2 which is the total of threshold voltages of a discharging circuit 43, the control circuit 4 activates the first control signal CT1 and operates the differential amplifier 101.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于半导体存储器并能够降低功耗的振荡器。 解决方案：当比较节点N1的电压V1变得大于第一参考电压Vref1时，振荡器1内的差分放大器101使脉冲发生电路110输出脉冲。 当脉冲输出时，比较节点N1由充电/放电电路105放电。此时，控制电路4使第一控制信号CT1失效，并停止差分放大器101.在比较节点N1被放电之后 由充电/放电电路105逐渐充电。结果，当电压V1超过作为放电电路43的阈值电压的总和的第二参考电压Vref2时，控制电路4激活第一控制信号CT1并操作 差分放大器101.版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003298397A

公开(公告)日：2003-10-17

申请号：JP2002086499

申请日：2002-03-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： YASUDA TAKAO

IPC: H03H17/00 ,  H03H17/06

Abstract: PROBLEM TO BE SOLVED: To provide a digital sample interpolator capable of reducing power consumption by simplifying the hardware.
SOLUTION: The digital sample interpolator 36 is provided with a shift register 38, an address generator 40 for collecting m sets of tap outputs for each of the same bit to generate a plurality of m-bit addresses, a look-up table 42 for outputting a corresponding partial product in response to the generated partial product, and a diagonal adder 34 for diagonally adding the outputted partial product. In this interpolator, the register 38 fetches an input data sample X in response to an input data clock IDC, and a multiplexer 46 delays the sample X in accordance with timing and outputs the sample X without any modification.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供能够通过简化硬件来降低功耗的数字采样插值器。 解决方案：数字采样内插器36设有移位寄存器38，地址发生器40，用于收集相同位中的每一个的m组抽头输出以产生多个m位地址，查找表 42，用于响应于所生成的部分乘积输出相应的部分乘积;以及对角线加法器34，用于对角地添加所输出的部分乘积。 在该内插器中，寄存器38响应于输入数据时钟IDC取出输入数据样本X，并且多路复用器46根据定时延迟样本X，并且不经任何修改地输出样本X. 版权所有（C）2004，JPO

公开(公告)号：JPH11185385A

公开(公告)日：1999-07-09

申请号：JP34236397

申请日：1997-12-12

Applicant: IBM

Inventor： KANAI TOSHIO ,  YASUDA TAKAO ,  TSURUTA KAZUHIRO ,  ICHIHARA WATARU

IPC: G11B7/005 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To reduce the influence of the interference between waveforms of a reproducing signal from a storage medium and to accurately binarize the reproducing signal. SOLUTION: This data slicing circuit 100, for binarizing a reproducing signal from a medium in which data are stored, including a peak detecting circuit 28 for detecting the peak value of the amplitude of reproducing signal from the medium, a threshold deciding circuit 28, for determining a compensating value for compensating the influence of the interference between waveforms of the reproducing signal based on the peak value detected by the peak detecting circuit and determining a threshold value for binarizing the reproducing signal based on the peak value and the compensating value, and a circuit 32 for binarizing the reproducing signal based on the threshold value decided by the threshold deciding circuit, is provided.