公开(公告)号：DE3063756D1

公开(公告)日：1983-07-21

申请号：DE3063756

申请日：1980-05-13

Applicant: IBM

Inventor： HEIMEIER HELMUT DR ,  KLEIN WILFRIED ,  KLINK ERICH ,  WERNICKE FRIEDRICH

IPC: G11C11/41 ,  G11C7/00 ,  G11C11/24 ,  G11C11/40 ,  G11C11/402 ,  G11C11/411 ,  G11C11/414 ,  G11C11/416

Abstract: Semiconductor storage in which the current necessary for reading and/or writing the storage cells is generated simply by discharging input capacitances of the non-selected storage cells and is fed directly to the selected storage cells for reading and/or writing.

公开(公告)号：DE3064212D1

公开(公告)日：1983-08-25

申请号：DE3064212

申请日：1980-04-25

Applicant: IBM

Inventor： HEIMEIER HELMUT DR ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH

IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416

Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

公开(公告)号：DE2926514A1

公开(公告)日：1981-01-15

申请号：DE2926514

申请日：1979-06-30

Applicant: IBM DEUTSCHLAND

Inventor： HEIMEIER HELMUT DR ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH

IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416 ,  G11C7/00

Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.