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    Method and structure for reducing power noise
    1.
    发明授权
    Method and structure for reducing power noise 失效
    降低功率噪声的方法和结构

    公开(公告)号：US6437252B2

    公开(公告)日：2002-08-20

    申请号：US74145500

    申请日：2000-12-19

    Applicant: IBM

    Inventor： REHM SIMONE ,  FRECH ROLAND ,  KLINK ERICH ,  VIRAG HELMUT ,  WINKEL THOMAS-MICHAEL ,  BECKER WIREN ,  CHAMBERLIN BRUCE ,  MA WAI

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/42

    CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

    Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

    Abstract translation: 描述了一种通过多个表面安装的去耦电容器来最小化印刷电路板或板上的高频和中频范围内的开关噪声的方法。 还介绍了包括连接通孔的电容器焊盘的新颖配置和实现。 结果，焊盘和通孔的寄生电感可以显着降低。 因此，可以提高中高频区域中的去耦电容器的有效性，可以降低电压降并且可以提高系统性能。 新焊盘通过配置的几个设计规则导致寄生电感的显着减少。 该建议对于板卡和卡上的高集成系统设计以及增加的周期时间尤其重要。

    IMPROVED WIRING STRUCTURE FOR HIGHLY EFFICIENT CHIP
    2.
    发明专利
    IMPROVED WIRING STRUCTURE FOR HIGHLY EFFICIENT CHIP 失效

    公开(公告)号：JPH10178016A

    公开(公告)日：1998-06-30

    申请号：JP29798897

    申请日：1997-10-30

    Applicant: IBM

    Inventor： FOLBERTH HARALD ,  KOEHL JUERGEN DR ,  KORTE BERNHARD PROF DR ,  KLINK ERICH

    IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528

    Abstract: PROBLEM TO BE SOLVED: To attenuate the inductive coupling and capacitive coupling between the conductors in each wiring layer by a method wherein each wiring direction of a plurality of wiring layers, which are stacked in multilayer, is rotated at the prescribed angle against the wiring direction of the wiring layer to be arranged in an induction and capacitive coupling region. SOLUTION: The wiring structures IIa and IIb, having seven superposed metal layers M0 to M6, which are superposed in multilayer, are formed by rotating at 45 deg. to 90 deg. with each other against the wiring direction of the wiring layer arranged in the relating inductive coupling region and a capacitive coupling region. Also, a wiring structure IIc, which is exceptional to the above- mentioned wiring structures IIa and IIb, is not interferentially coupled between the wiring structures of the metal layers M1 and M2 on the metal layers M3, M4, M5 and M6, and low interferential voltage, which can be neglected, is grown. As a result, the inductive coupling and the capacitive coupling between the conductors in each wiring layer can be lessened, and a highly efficient chip can be obtained.

    TWO-STAGE POWER NOISE FILTER
    3.
    发明专利
    TWO-STAGE POWER NOISE FILTER 失效

    公开(公告)号：JPH11354724A

    公开(公告)日：1999-12-24

    申请号：JP33881398

    申请日：1998-11-30

    Applicant: IBM

    Inventor： FRECH ROLAND DR ,  KLINK ERICH ,  SHUTLER WILLIAM ,  WEISS ULRICH ,  WINKEL THOMAS-MICHAEL

    IPC: H01G4/40 ,  H01L21/822 ,  H01L25/00 ,  H01L27/04 ,  H03L7/099 ,  H04B15/00

    Abstract: PROBLEM TO BE SOLVED: To reduce power noise by connecting a first low pass filter which has an off-chip capacitance and filtrates intermediate-frequency power noise, and a second low pass filter which has an on-chip capacitance and filtrates high-frequency power noise in series. SOLUTION: A first low pass filter which filtrates intermediate-frequency power noise having a frequency of 10-100 MHz is composed of an off-chip capacitance 2, an on-chip resistor R16 which connects a voltage surface VDD to an in-chip node 18, and thin film wiring 8 in the uppermost layer of a multilayered thin film. A second low pass filter which filtrates high-frequency power noise is composed of an on-chip capacitance 12 and an on-chip resistor 7. The first and second low pass filters are connected in series. The first low pass band stage backs up the low induced charge of the capacitance 12 of the second low pass filter and the second low pass band stage becomes the low induced current source of a voltage-controlled device.

    Multilayer module
    4.
    发明专利
    Multilayer module 有权
    多层模块

    公开(公告)号：JP2005223332A

    公开(公告)日：2005-08-18

    申请号：JP2005026945

    申请日：2005-02-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FRECH ROLAND DR ,  GARBEN BERND DR ,  KLINK ERICH ,  OGGIONI STEFANO

    IPC: H01L23/12 ,  H01L23/498 ,  H05K1/00 ,  H05K1/02

    CPC classification number: H05K1/0216 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/09327 ,  H05K2201/10522 ,  H05K2201/10734

    Abstract: PROBLEM TO BE SOLVED: To increase the importance of a future microprocessor and a future computer system by decreasing power noise of intermediate frequency, by providing a semiconductor device structure for improving power noise property, and to provide a multilayer module having superior electrical characteristics accompanying reduction in the manufacturing cost, increase in wiring capability, and decrease in inductance. SOLUTION: A multilayer module comprises a top conductive layer L1 to which an electronic component is attached, a plurality of insulating layers 6, and a plurality of conductive layers L2-L8 arranged between the insulating layers. As for the conductive layers L1-L4 near the front surface of the module, two of at least three layers, a potential layer and/or a ground layer, are arranged alternately such that a signal layer is not sandwiched by the layers. Further, the multilayer module has a via, by which a corresponding signal layer, the potential layer, and the ground layer are electrically connected with each another and also with the top conductive layer L1. Further, the multilayer module has two layers of the potential layer and the ground layer, arranged alternately near the front surface, so that there is no signal layer therebetween, and a structure in which the via is not arranged in a local region for attaining the electrical effects of a solid surface. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：通过提供用于提高功率噪声性能的半导体器件结构，通过降低中频功率噪声来增加未来微处理器和未来计算机系统的重要性，并提供具有优异电气的多层模块 随着制造成本的降低，接线能力的增加和电感的降低。 解决方案：多层模块包括安装电子部件的顶部导电层L1，多个绝缘层6和布置在绝缘层之间的多个导电层L2-L8。 对于在模块前表面附近的导电层L1-L4，交替地布置至少三层中的至少三层，即电位层和/或接地层，使得信号层不被层夹在中间。 此外，多层模块具有通孔，相应的信号层，电位层和接地层彼此电连接，并且还与顶部导电层L1电连接。 此外，多层模块具有两层电位层和接地层，交替地布置在前表面附近，使得它们之间不存在信号层，并且其中通孔不被布置在局部区域中以获得 固体表面的电气效应。 版权所有（C）2005，JPO＆NCIPI

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