中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.016 seconds)

    1.
    发明专利
    未知

    公开(公告)号：FR2335909A1

    公开(公告)日：1977-07-15

    申请号：FR7634520

    申请日：1976-11-08

    Applicant: IBM

    Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WIEDMANN SIEGFRIED

    IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

    Abstract: An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (first level) flows from the load elements to the internal cell nodes in the stand-by mode. During the initial portion of a read cycle, current flows from the bit lines to the cell nodes, in addition to the stand-by current (second level). In the recovery period of the read cycle or write cycle a short pulse is added to the stand-by current (third level), thereby reducing the recovery time. The practice of the invention provides a monolithic memory having minimal power requirements and a substantially reduced cycle time.

    2.
    发明专利
    未知

    公开(公告)号：FR2312836A1

    公开(公告)日：1976-12-24

    申请号：FR7610165

    申请日：1976-04-01

    Applicant: IBM

    Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  REMSHARDT ROLF

    IPC: G11C11/41 ,  G11C11/413 ,  G11C11/415 ,  H03K19/088 ,  H03M7/00 ,  G11C7/00 ,  G11C11/40

    Abstract: A method and circuit arrangement for operating an information store, in particular a monolithic information store, whose storage cells and address circuits comprise bipolar transistors which are not continuously subjected to full power. The monolithic information store is readily fabricated by known planar process technology, has increased density, has reduced read/write times, reduced cycle time, and reduced power dissipation.

    ELECTRICAL MEMORY DEVICE AND ITS METHOD OF OPERATION
    3.
    发明专利
    ELECTRICAL MEMORY DEVICE AND ITS METHOD OF OPERATION 未知

    公开(公告)号：DE3064212D1

    公开(公告)日：1983-08-25

    申请号：DE3064212

    申请日：1980-04-25

    Applicant: IBM

    Inventor： HEIMEIER HELMUT DR ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH

    IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416

    Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

    4.
    发明专利
    未知

    公开(公告)号：DE2926514A1

    公开(公告)日：1981-01-15

    申请号：DE2926514

    申请日：1979-06-30

    Applicant: IBM DEUTSCHLAND

    Inventor： HEIMEIER HELMUT DR ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDRICH

    IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416 ,  G11C7/00

    Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

    5.
    发明专利
    未知

    公开(公告)号：FR2295524A1

    公开(公告)日：1976-07-16

    申请号：FR7534718

    申请日：1975-11-05

    Applicant: IBM

    Inventor： HEUBER KLAUS ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  REMSHARDT ROLF

    IPC: G11C11/41 ,  G11C11/34 ,  G11C11/416 ,  H03K3/287 ,  H03K5/02 ,  G11C7/00 ,  G11C11/40

    Abstract: This teaches a sense circuit for an integrated memory storage system in which the storage cell output is detected by a differential amplifier, controlling a flip-flop, serving as a latch, having load elements which also function as the load elements of the latch to ensure an optimum power and speed product. The latch can be coupled to an output driver circuit through a current switch which shares common elements with the latch to assure that the latch remains symmetrical even when used with an output driver having asymmetrical control.

    6.
    发明专利
    未知

    公开(公告)号：IT1149977B

    公开(公告)日：1986-12-10

    申请号：IT2271680

    申请日：1980-06-11

    Applicant: IBM

    Inventor： HEIMER HELMUT H ,  KLEIN WILFRIED ,  NAJMANN KNUT ,  WERNICKE FRIEDERICH C

    IPC: G11C11/41 ,  G11C7/02 ,  G11C7/06 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C11/40 ,  G11C11/4091 ,  G11C11/416

    Abstract: An integrated semiconductor memory having memory cells which have (or are designed to have) inherent asymmetrical access times for the distinguishable memory states thereof. The memory is operated on the basis of the shorter access time. This is accomplished by utilizing an oppositely asymmetrical sense system, preferably in the form of a pre-set sense latch. For example, in the case of a digital memory with the reading of a "0" state having a shorter access time than the reading of a "1" state, at the beginning of a read operation a sense latch is set to the (slower) "1" state. Thus, only in the case of reading a "0" is the state of the latch changed to the "0" state. Thus, the actual access time is no longer determined by the longer access time, namely, the reading of a "1". The access time is determined by the shorter access time, namely, the reading of a "0". The concept may also be used if the sense latch has an asymmetric access time. Then it is advantageous to intentionally choose a corresponding asymetrical memory cell design.

Patent Agency Ranking