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    COMPUTER SYSTEM FOR IMPROVING SYSTEM PERFORMANCE WITH PIPELINE SYNCHRONISM
    1.
    发明专利
    COMPUTER SYSTEM FOR IMPROVING SYSTEM PERFORMANCE WITH PIPELINE SYNCHRONISM 失效

    公开(公告)号：JP2000347859A

    公开(公告)日：2000-12-15

    申请号：JP2000126367

    申请日：2000-04-26

    Applicant: IBM

    Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

    IPC: G06F12/08 ,  G06F9/38 ,  G06F15/16 ,  G06F15/80

    Abstract: PROBLEM TO BE SOLVED: To reduce the disadvantage of a finite cache and to improve system performance by processing an inference process through an inference engine processing element(PE) and improving the disadvantage of the finite cache detected by a conventional PE. SOLUTION: First PE μm PCore 200, 200' and 200" process the instructions of a successive instruction stream in proper order and control an architecture state. The processing of successive instruction stream is performed while using the first PE μm PCore 200, 200' and 200" for transferring the change in the architecture state of a computer system to second PE SFE 202, 202' and 202". When it is advantageous to make the second PE such as SFE 202 start the continuous processing of the same successive instruction stream at any arbitrary time point during the processing of successive instruction stream due to the first PE such as μm PCore 200, however, the second PE SFE 200 restores the transferred state and processes the successive instruction stream.

    Method, computer program, and apparatus for creation and management of routing table for pci bus address based routing with integrated did
    3.
    发明专利
    Method, computer program, and apparatus for creation and management of routing table for pci bus address based routing with integrated did 审中-公开
    方法，计算机程序和设备，用于创建和管理基于PCI总线地址的路由表与集成DID

    公开(公告)号：JP2007195166A

    公开(公告)日：2007-08-02

    申请号：JP2006348980

    申请日：2006-12-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RENATO J RECIO ,  STEVEN WADE HUNTER ,  BOYD WILLIAM TODD ,  THURBER STEVEN MARK ,  MADELINE VEGA ,  HOLLAND WILLIAM G ,  FREIMUTH DOUGLAS M

    IPC: H04L12/28

    CPC classification number: G06F13/4022 ,  H04L45/00 ,  H04L45/54

    Abstract: PROBLEM TO BE SOLVED: To share PCI adapters between multiple blades.
    SOLUTION: The present invention relates to a method for routing PCI transaction packets through switches between hosts and adapters in a distributed computing system that includes multiple route nodes, one or more PCI switches and PCI adapters, wherein each route node includes multiple hosts and one of the route nodes includes a PCI configuration manager (PCM). A table is created within specified one of switches and when a particular host is connected to the specified switch, a destination identifier including a set of bits designated by operating the PCM is entered to the table. The destination identifier is appended as an address to PCI packet directed through the specified switch from the particular host to one of the adapters. The destination identifier is used to determine that a PCI packet, routed through the specified switch from one of the adapters, is intended for the particular host.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：在多个刀片之间共享PCI适配器。 解决方案：本发明涉及一种用于在包括多个路由节点，一个或多个PCI交换机和PCI适配器的分布式计算系统中的主机和适配器之间的交换机路由PCI事务分组的方法，其中每个路由节点包括多个主机 并且其中一个路由节点包括PCI配置管理器（PCM）。 在指定的一个交换机内创建表，当特定主机连接到指定的交换机时，包括通过操作PCM指定的一组位的目的地标识符被输入到表中。 将目的地标识符作为地址提供给通过指定交换机从指定主机指向其中一个适配器的PCI数据包。 目的地标识符用于确定通过指定交换机从其中一个适配器路由的PCI数据包是针对特定主机的。 版权所有（C）2007，JPO＆INPIT

    Sequential instruction stream processing method, computer system and microprocessor
    4.
    发明专利
    Sequential instruction stream processing method, computer system and microprocessor 审中-公开
    顺序指令流程处理方法，计算机系统和微处理器

    公开(公告)号：JPH11272482A

    公开(公告)日：1999-10-08

    申请号：JP597399

    申请日：1999-01-13

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

    Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

    IPC: G06F9/38 ,  G06F9/34 ,  G06F9/46 ,  G06F15/16

    Abstract: PROBLEM TO BE SOLVED: To reduce the disadvantage of a finite cache and to improve system performance by changing a whole architecture state only in a first or second processing element.
    SOLUTION: When it becomes advantageous that the continuous processing of a sequential instruction stream is started by a second processing element 202 at arbitrary time during the processing of the sequential instruction stream by a first processing element 200, the second processing element restores a transferred state and the second processing element processes the sequential instruction stream. Thus, the continuous processing of the same sequential instruction stream is started. Then, the second processing element transfers the change of the architecture state of a computer system which the first processing element requests to the first processing element. Only the first or the second processing element can change the whole architecture state of the computer system decided by the combination of the states of the first and second processing elements.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：为了减少有限缓存的缺点，并且仅通过在第一或第二处理元件中改变整个架构状态来提高系统性能。 解决方案：当在第一处理单元200处理顺序指令流期间的任意时刻连续处理顺序指令流是有利的时候，第二处理单元恢复转移状态， 第二处理元件处理顺序指令流。 因此，开始连续处理相同的顺序指令流。 然后，第二处理单元将第一处理单元要求的计算机系统的体系结构状态的变更传递给第一处理单元。 只有第一或第二处理元件可以改变由第一和第二处理元件的状态的组合决定的计算机系统的整体架构状态。

    Improvements for a microprocessor with pipeline synchronization
    5.
    发明专利
    Improvements for a microprocessor with pipeline synchronization 未知

    公开(公告)号：SG77216A1

    公开(公告)日：2000-12-19

    申请号：SG1999000119

    申请日：1999-01-20

    Applicant: IBM

    Inventor： HELLER THOMAS J JR ,  BOYD WILLIAM TODD

    IPC: G06F9/38

    Abstract: A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of said processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have said second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements. The second processor will have more pipeline stages than the first in order processor to feed the first processor and reduce the finite cache penalty and increase performance. The processing and storage of results of the second processor does not change the architectural state of the computer system. Results are stored in its gprs or its personal storage buffer. Resynchronization of states with a coprocessor occurs upon an invalid op, a stall or a computed specific benefit to processing with the coprocessor as a speculative coprocessor. In an alternative embodiment the foregoing process is generalized for both processors allowing processors to forward and store architectural state changes for future use as required by the other processor when at a later time the processor which is permitted to change the overall architectural state of said computer system is changed.

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