公开(公告)号：GB2529862A

公开(公告)日：2016-03-09

申请号：GB201415669

申请日：2014-09-04

Applicant: IBM

Inventor： SAUTTER ROLF ,  FRITSCH ALEXANDER ,  KUGEL MICHAEL ,  HELLNER GERHARD

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/08 ,  G11C11/413 ,  G11C15/04

Abstract: Electronic circuit comprising a current sense amplifier 103 and static memory cells 115. The current sense amplifier comprises a reference current input terminal 109, a sense current input terminal 108, and an output terminal 106, the static memory cells being coupled in parallel each via a respective associated n-FET stack 116 (i.e n-type MOSFET devices connected in series) to the sense current input terminal, the reference current input terminal being coupled to ground via two reference n-FET stacks 127 connected in series, the amplifier being configured to: generate a first logical value at the output terminal, in response to a reference current of the reference current input being higher than a sense current of the sense current input terminal, and generate a second logical value at the output terminal, in response to a reference current of the reference current input terminal being lower than a sense current of the sense current input terminal. A voltage generator 129 (or Vdd supply) may be coupled to the gate terminals of n-FET stacks to form a current source (current sink). Preferably each of the static memory cells comprises a data output coupled to a gate of at least one transistor in the n-FET stack. The current in the reference n-FET stacks should be less than the grounding current in the sense n-FET stack, ideally one half the value of the sense side grounding current for optimum detection. In one embodiment (figure 7) the static memory cells are configured in pairs to form Ternary Content Addressable Memories (TCAM), whereby the TCAM word lines (118A,B, figure 7) connect to a gate of the N-FET sense stacks, allowing the memory cells access to the current sense input 108. The reference current source in this embodiment utilises four n-FET stacks. The current sense amplifier (figure 1) may comprise a current latched sense amplifier (CLSA) having NAND gates connected to each output of a cross coupled inverter pair enabled by a control input signal (125, figure 1) and a transmission gate connecting the two inverter output nodes, enabled also by the control signal (125).