公开(公告)号：GB2529862A

公开(公告)日：2016-03-09

申请号：GB201415669

申请日：2014-09-04

Applicant: IBM

Inventor： SAUTTER ROLF ,  FRITSCH ALEXANDER ,  KUGEL MICHAEL ,  HELLNER GERHARD

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/08 ,  G11C11/413 ,  G11C15/04

Abstract: Electronic circuit comprising a current sense amplifier 103 and static memory cells 115. The current sense amplifier comprises a reference current input terminal 109, a sense current input terminal 108, and an output terminal 106, the static memory cells being coupled in parallel each via a respective associated n-FET stack 116 (i.e n-type MOSFET devices connected in series) to the sense current input terminal, the reference current input terminal being coupled to ground via two reference n-FET stacks 127 connected in series, the amplifier being configured to: generate a first logical value at the output terminal, in response to a reference current of the reference current input being higher than a sense current of the sense current input terminal, and generate a second logical value at the output terminal, in response to a reference current of the reference current input terminal being lower than a sense current of the sense current input terminal. A voltage generator 129 (or Vdd supply) may be coupled to the gate terminals of n-FET stacks to form a current source (current sink). Preferably each of the static memory cells comprises a data output coupled to a gate of at least one transistor in the n-FET stack. The current in the reference n-FET stacks should be less than the grounding current in the sense n-FET stack, ideally one half the value of the sense side grounding current for optimum detection. In one embodiment (figure 7) the static memory cells are configured in pairs to form Ternary Content Addressable Memories (TCAM), whereby the TCAM word lines (118A,B, figure 7) connect to a gate of the N-FET sense stacks, allowing the memory cells access to the current sense input 108. The reference current source in this embodiment utilises four n-FET stacks. The current sense amplifier (figure 1) may comprise a current latched sense amplifier (CLSA) having NAND gates connected to each output of a cross coupled inverter pair enabled by a control input signal (125, figure 1) and a transmission gate connecting the two inverter output nodes, enabled also by the control signal (125).

公开(公告)号：GB2512641A

公开(公告)日：2014-10-08

申请号：GB201306122

申请日：2013-04-05

Applicant: IBM

Inventor： POLIG RAPHAEL ,  WERNER TOBIAS ,  PENTH SILKE ,  KUGEL MICHAEL

IPC: G11C8/10 ,  G11C8/08 ,  G11C8/12

Abstract: An SRAM array 100 comprising multiple cell cores 102, 104, 106, 108 to store and retrieve data, each cell core comprising a plurality of SRAM cells 112, and wherein at least two corresponding cell cores 102, 104 and 106, 108 build a cell core row 122. A word decoder 110 configured to decode incoming address signals 116 representing a storage address into a single word line 114, so that one storage word is activated. The word decoder 110 comprises, a cell core select unit (306, figure 3) configured to generate a cell core row select signal (402, figure 4) from a combination of a first part (412) of the incoming address signals 116 and a received clock signal (308, figure 4), a decoding element (302, 304, figure 4) for each cell core row 122, the decoding element comprising a first decoding block (404, figure 4) for decoding a second part (414, figure 4) of the incoming address signals 116 for building an upper portion (408) of word line select signals (422) and a second decoding block (406 figure 4) for decoding a third part (416) of the incoming address signals 116 for building a lower portion (410, figure 4) of word line select signals (422), a word line driver (418, 420) for each cell core row (122) configured to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unique word line signal 114 per storage address.

公开(公告)号：GB2529861A

公开(公告)日：2016-03-09

申请号：GB201415668

申请日：2014-09-04

Applicant: IBM

Inventor： FRITSCH ALEXANDER ,  KUGEL MICHAEL ,  PILLE JUERGEN ,  WENDEL DIETER

IPC: G11C7/06 ,  G11C7/08 ,  G11C8/08 ,  G11C11/419

Abstract: A current latched sense amplifier CSLA 103 comprising a reference current input terminal (109), a control line input terminal 125, a sense current input terminal 108, an output terminal 106, a first NAND gate 100, a transmission gate 104, and two cross coupled inverters T1, T2, T3, T4 each comprising an nMOSFET device T2, T4. The first NAND gate 100 comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate 104 comprises two transmission terminals and a gate terminal which is coupled to the control line terminal 125. Sources of the n-MOSFETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively. The gate terminal of the transmission gate allows for on/off switching. A first inverter 102 couples one of the input terminals of the first NAND gate to the control line 125. A second NAND gate may be coupled to the second terminal of the amplifier, having a second input controlled by the output of the inverter 102. An electronic circuit may also be included which comprises static memory cells and the current sense amplifier (or current latched sense amplifier). Static Memory Cells may be arranged (figure 4 or 5) such that the data output of each of the cells is coupled via an nMOSFET stack (116 Figure 4) to the sense input of the current sense amplifier.

公开(公告)号：GB2507754A

公开(公告)日：2014-05-14

申请号：GB201220087

申请日：2012-11-07

Applicant: IBM

Inventor： WERNER TOBIAS ,  PAYER STEFAN ,  POLIG RAPHAEL ,  KUGEL MICHAEL

IPC: G06F17/50

Abstract: The application relates to scalable circuit schematic. A computer-readable memory comprises first data representative of a topology of a circuit comprising a first circuit clement and a second circuit element, and second data representative of a scaling rule for the first circuit clement as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit clement and a second circuit clement from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function or the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data. The scaling rule may be for a capacitance as a function of load, resistance as a function of a transistor, a transistor as a function of resistance or a transistor as a function of another transistor.