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    Delaying the stop-clock signal of a chip by a set amount of time so that error handling and recovery can be performed before the clock is stopped
    1.
    发明专利
    Delaying the stop-clock signal of a chip by a set amount of time so that error handling and recovery can be performed before the clock is stopped 未知

    公开(公告)号：GB2456618A

    公开(公告)日：2009-07-22

    申请号：GB0822285

    申请日：2008-12-08

    Applicant: IBM

    Inventor： KOENIG ANDREAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  BUECHNER THOMAS

    IPC: G06F11/07

    Abstract: Disclosed is a method and circuit for operating self-checking logic 16, 18, 28 in a computer processing chip 10. The chip has functional units for detecting errors 28, for tracing the errors 18, and for controlling the processor clock 16, such that a clock-stop signal is generated by the self-checking logic which is used for error management and recovery. When a stop-clock signal is generated the signal is intercepted 440, a delay 445 is defined during which error-related, chip internal error handling and/ or recovery preparation actions are processed 470. At the end of the predetermined delay 460 the clock-stop action is performed 490, 495. A warning message to firmware may be sent to help in error and recovery management. The delay may be configured according to the location of the failure, the time needed to communicate with the stop-clock signal to the clock mechanism on the chip and/or the time needed to collect and store debug data.

    Request filtering in multi-stage arbiter circuitry to reduce latency
    4.
    发明专利
    Request filtering in multi-stage arbiter circuitry to reduce latency 未知

    公开(公告)号：GB2454818A

    公开(公告)日：2009-05-20

    申请号：GB0822309

    申请日：2008-12-08

    Applicant: IBM

    Inventor： HELMS MARKUS ,  SENTLER DANIEL ,  WALZ MANFRED

    IPC: G06F13/364 ,  G06F13/30

    Abstract: Arbiter circuitry 11 includes at least one request filter 12, a plurality of requestor latches 14, at least two staged arbiters 13 arranged directly behind the requestor latches, and an arbitration result latch 15 arranged behind the arbiters. Request filter 12 is arranged behind the arbitration result latch 15 in a non-timing critical path, e.g. pipeline stage 16. A latency reduction is achieved by avoiding stage latches (06, fig. 1). Moving filter 12 to pipeline stage 16 means that incorrect arbitration results may occur so, preferably, it is possible to rollback incorrect arbitration results. To allow rollback, two-staged grants may be provided, e.g. a preliminary grant (22) in a first cycle and a final grant (24) in a second cycle. Preferably, arbitration circuitry 11 is operated below its maximum throughput capacity. The invention may be applied to processing direct memory access (DMA) requests of input/output (I/O) devices attached to an I/O adapter of a host device having main memory.

    Multiprocessor system with synchronization of error recovery to prevent errors spreading
    8.
    发明专利
    Multiprocessor system with synchronization of error recovery to prevent errors spreading 未知

    公开(公告)号：GB2456403A

    公开(公告)日：2009-07-22

    申请号：GB0822313

    申请日：2008-12-08

    Applicant: IBM

    Inventor： KOENIG ANDREAS ,  SCHLIPF THOMAS ,  KLEIN MATTHIAS ,  WALZ MANFRED ,  FRITZ ROLF

    IPC: G06F11/07

    Abstract: A method of operating self-testing logic in a tree-like multi-chip processor cluster which generates an infrastructure signal 430, such as a clockstop or tracestop signal, used for error management and recovery. The operation intercepts 440 the infrastructure signal of a processor of the cluster then extracts error information from the infrastructure signal. Using the error information a pre-defined inter-chip error synchronisation scheme is selected 450 including clock-stop and/or trace-stop information for a respective one of the processors of the cluster. Notification signals are distributed 490 to chips of the cluster using dedicated wires or a low-level standard interface for chip-to-chip communication to prepare and execute error related internal operations for chips. On receipt of one of the notification signals a chip performs at least one of (i) performing a trace-stop command or (ii) performing a clock-stop command 495 on a respective one of the chips as derived from the synchronisation scheme. The synchronisation scheme may comprise a configurable delay adjustable according to the location of the failure within the chip.

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