公开(公告)号：DE2001664A1

公开(公告)日：1970-07-23

申请号：DE2001664

申请日：1970-01-15

Applicant: IBM

Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  HENRY SUSSENGUTH EDWARD

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/16

Abstract: 1282341 Data processing INTERNATIONAL BUSINESS MACHINES CORP 12 Jan 1970 [15 Jan 1969] 1358/70 Heading G4A In stored-program data processing apparatus, switching to another instruction stream as a result of a successful conditional branch instruction occurs after execution of a marker instruction. Instructions are accessed from memory and inserted into the top of a multi-instruction pushdown buffer together with bits indicating, for each instruction, whether or not it is a target, branch or exit instruction. The target bit is provided at the memory (see below) and the branch and exit bits are derived by a predecoder. The instruction at the bottom of the buffer is decoded. If it is a branch instruction, two fields in it select two bits from a condition register and 1 of 8 logical functions of these specified by part of the op code is evaluated in a function generator to determine whether the branch should be taken, the branching being to an address obtained by adding a field from the instruction and the contents of one of a plurality of registers selected by another field of the instruction. However, the sequence of instruction fetching branches to this address only when the next exit instruction enters the buffer. The branched-to instruction has its target bit set to 1 at the memory. Decoding and therefore execution of each instruction in the buffer between the exit instruction and the target instruction is inhibited, the inhibition terminating when the target instruction is shifted into the bottom position of the buffer, in response to the target bit of 1. Decoding of any branch instruction after a successful branch instruction and before the next exit instruction is also inhibited. If both an exit and a branch instruction are present in the buffer but a successful branch has not been determined, instruction fetching is suspended until not all these conditions exits, thus awaiting the result of the branch test. Instruction fetching is from the next sequential address if there is no exit instruction in the buffer, and if there is but there is neither a branch instruction in the buffer nor an indication of a successful branch determined.

公开(公告)号：DE2131066A1

公开(公告)日：1972-01-05

申请号：DE2131066

申请日：1971-06-23

Applicant: IBM

Inventor： FAIRBANKS ARNOLD RICHARD ,  SIMON DAUBER PHILIP ,  HENRY SUSSENGUTH EDWARD

IPC: G06F12/10 ,  G06F9/20

Abstract: A directory, or index, of variable-sized pages of data for use in a two-level storage system employing virtual addressing, wherein data is stored in a large capacity main storage and retrieved to a smaller, faster buffer storage for processing. If a desired piece of data indicated by a virtual address is not currently resident in buffer storage, the location of the beginning of the page containing that data in main storage is found by searching the directory. Directory addresses for searching the directory are formed by a pseudo-random function of two parameters, the virtual address and a count. Since a larger page-size entry will be addressed statistically more frequently than a smaller page-size entry, a new directory entry for a given page size is made in the first location along its algorithm chain which currently contains either an invalid entry or a smaller page-size entry. Thus, it may be necessary to relocate a smaller page-size entry further down its chain.