中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.017 seconds)

    Hierarchical memory updating system
    1.
    发明授权
    Hierarchical memory updating system 失效
    分层记忆更新系统

    公开(公告)号：US3588839A

    公开(公告)日：1971-06-28

    申请号：US3588839D

    申请日：1969-01-15

    Applicant: IBM

    Inventor： BELADY LASZLO A ,  KUEHNER CARL J ,  LEHMAN MEIR M ,  RANDELL BRIAN

    IPC: G06F12/08 ,  G11C9/00 ,  G11C7/00

    CPC classification number: G06F12/0804

    Abstract: A COMPUTER MEMORY SYSTEM IN WHICH THE DATA IS TRANSFERRED BETWEEN HIGH-SPEED LOCAL STORAGE AND ONE OR MORE LEVELS OF A LARGER LOW SPEED STORAGE WHEREIN ALTERED DATA IS REWRITTEN IN HIGH-SPEED STORAGE IMMEDIATELY AND IN THE LOWSPEED STORAGE ON A CYCLE STEALING BASIS. CONTROLS ARE PROVIDED SO THAT WHEN A SMALL SEGMENT OF DATA IN A PARTICULAR BLOCK OR PAGE IN HIGH-SPEED STORE IS ALTERED AND INDICATOR IS SET. WHEN MEMORY BUSS TIME IS AVAILABLE TO THE LOW SPEED OR BACKUP STORE THESE INDICATORS WILL BE CHECKED AND WORDS OR LINES REWRITTEN IN SAID BACKUP STORE AS LONG AS A HIGHER PRIORITY JOB IS NOT ENCOUNTERED. WHEN IT IS DESIRED TO REPLACE A COMPLETE PAGE IN HIGH-SPEED STORAGE, INDICATORS FOR THAT PAGE ARE CHECKED AND ALL ALTERED WORDS ARE REWRITTEN IMMEDIATEDLY IN THE BACKUP STORE ON A HIGH PRIORITY BASIS AFTER WHICH THE PAGE IN THE HIGH-SPEED STORE MAY BE OVERWRITTER WITH NEW DATA FROM THE BACKUP STORE.

    6.
    发明专利
    未知

    公开(公告)号：DE2001664A1

    公开(公告)日：1970-07-23

    申请号：DE2001664

    申请日：1970-01-15

    Applicant: IBM

    Inventor： COCKE JOHN ,  RANDELL BRIAN ,  SCHORR HERBERT ,  HENRY SUSSENGUTH EDWARD

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/16

    Abstract: 1282341 Data processing INTERNATIONAL BUSINESS MACHINES CORP 12 Jan 1970 [15 Jan 1969] 1358/70 Heading G4A In stored-program data processing apparatus, switching to another instruction stream as a result of a successful conditional branch instruction occurs after execution of a marker instruction. Instructions are accessed from memory and inserted into the top of a multi-instruction pushdown buffer together with bits indicating, for each instruction, whether or not it is a target, branch or exit instruction. The target bit is provided at the memory (see below) and the branch and exit bits are derived by a predecoder. The instruction at the bottom of the buffer is decoded. If it is a branch instruction, two fields in it select two bits from a condition register and 1 of 8 logical functions of these specified by part of the op code is evaluated in a function generator to determine whether the branch should be taken, the branching being to an address obtained by adding a field from the instruction and the contents of one of a plurality of registers selected by another field of the instruction. However, the sequence of instruction fetching branches to this address only when the next exit instruction enters the buffer. The branched-to instruction has its target bit set to 1 at the memory. Decoding and therefore execution of each instruction in the buffer between the exit instruction and the target instruction is inhibited, the inhibition terminating when the target instruction is shifted into the bottom position of the buffer, in response to the target bit of 1. Decoding of any branch instruction after a successful branch instruction and before the next exit instruction is also inhibited. If both an exit and a branch instruction are present in the buffer but a successful branch has not been determined, instruction fetching is suspended until not all these conditions exits, thus awaiting the result of the branch test. Instruction fetching is from the next sequential address if there is no exit instruction in the buffer, and if there is but there is neither a branch instruction in the buffer nor an indication of a successful branch determined.

    7.
    发明专利
    未知

    公开(公告)号：DE1965506A1

    公开(公告)日：1970-07-16

    申请号：DE1965506

    申请日：1969-12-30

    Applicant: IBM

    Inventor： RANDELL BRIAN

    IPC: G06F9/32 ,  G06F9/38 ,  G06F9/20

    Abstract: 1,235,638. Computers. INTERNATIONAL BUSINESS MACHINES CORP. 1 Jan., 1970 [6 Jan., 1969], No. 130/70. Heading G4A. A computer system transfers work data between a work register and a data store location specified by address data as modified by index data, both address data and index data coming from the work register, and increments the index data. Local-storage work registers each contain a data field, an index field and an address field. An instruction for an execute operation specifies two of the registers to supply operands and one to receive the result, and contains a tag bit for each. If this tag bit for an operand is 1, then after gating the operand to the arithmetic logic unit, another operand is loaded into the register from the main store location specified by the sum of the address and index fields from the register and the index field is incremented and restored, these reload and increment operations being omitted if the tag bit is 0. If the tag bit for the result is 1, then after gating the result to the work register, the result is stored in the main memory with addressing and incrementing as above, these store and increment operations being omitted if the tag bit is 0. Thus an instruction can be executed repeatedly using different operands. Two-bit tags could be used to permit selection of a load or store operation. The address fields could select index registers providing the addresses.

Patent Agency Ranking