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公开(公告)号：CA2130408A1
公开(公告)日：1995-05-18
申请号：CA2130408
申请日：1994-08-18
Applicant: IBM
Inventor： FUOCO DANIEL P , HERRING CHRISTOPHER M , KELLOGG MARK W , LENTO JORGE E
Abstract: A computer system and method of using the same is provided which system has a CPU, a bus, and add-on memory. The CPU has parity generation and detection capabilities but does not necessarily have error correction capabilities. The present invention provides error correction capabilities in add-on memory or in association with the add-on memory which allows error correction of single bit read errors from the add-on memory and also allows for the detection of multiple bit read errors and the detection of write errors by byte location of the write errors.
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公开(公告)号：CA2130406A1
公开(公告)日：1995-05-18
申请号：CA2130406
申请日：1994-08-18
Applicant: IBM
Inventor： FUOCO DANIEL P , HERRING CHRISTOPHER M , KELLOGG MARK W , LENTO JORGE E
Abstract: ERROR CORRECTION CODE ON ADD-ON CARDS FOR WRITING PORTIONS OF DATA WORDS The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the addon memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.
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公开(公告)号：CA2130405A1
公开(公告)日：1995-05-18
申请号：CA2130405
申请日：1994-08-18
Applicant: IBM
Inventor： FUOCO DANIEL P , HERRING CHRISTOPHER M , KELLOGG MARK W , LENTO JORGE E
Abstract: The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic. Also provided is a circuitry card technique to block or by-pass error reporting and correcting during initialization.
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