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公开(公告)号：CA2064162A1
公开(公告)日：1992-11-29
申请号：CA2064162
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40 , G06F13/20
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：CA2130408A1
公开(公告)日：1995-05-18
申请号：CA2130408
申请日：1994-08-18
Applicant: IBM
Inventor： FUOCO DANIEL P , HERRING CHRISTOPHER M , KELLOGG MARK W , LENTO JORGE E
Abstract: A computer system and method of using the same is provided which system has a CPU, a bus, and add-on memory. The CPU has parity generation and detection capabilities but does not necessarily have error correction capabilities. The present invention provides error correction capabilities in add-on memory or in association with the add-on memory which allows error correction of single bit read errors from the add-on memory and also allows for the detection of multiple bit read errors and the detection of write errors by byte location of the write errors.
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公开(公告)号：BR9201917A
公开(公告)日：1993-01-12
申请号：BR9201917
申请日：1992-05-21
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
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公开(公告)号：BR9201974A
公开(公告)日：1993-01-12
申请号：BR9201974
申请日：1992-05-26
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
IPC: G06F13/18 , G06F13/36 , G06F13/362 , G06F13/14
Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.
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公开(公告)号：CA2067602A1
公开(公告)日：1992-11-29
申请号：CA2067602
申请日：1992-04-29
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
IPC: G06F13/18 , G06F13/36 , G06F13/362 , G06F13/20
Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.
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Patent Agency Ranking
公开(公告)号：MX9202526A
公开(公告)日：1992-11-01
申请号：MX9202526
申请日：1992-05-28
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS ANTONIO , MATHISEN ERIC , MOELLER DENNIS LEE , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
IPC: G06F13/362 , G06F13/40 , G06K9/26
Abstract: This invention relates to personal computers, and more particularly to personal computers in which performance is enhanced by enabling arbitration for control over a local processor bus among a plurality of "master" devices coupled directly to the local processor bus. A personal computer system in accordance with this invention has a high speed local processor data bus; an input/output data bus; at least two master devices coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus, with the bus interface controller providing for arbitration among the master devices coupled directly to the local processor bus for access to the local processor bus, and providing for arbitration among the local processor bus and any devices coupled directly to the input/output data bus for access to the input/output data bus.
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公开(公告)号：CA2064163C
公开(公告)日：1998-04-14
申请号：CA2064163
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , RAYMOND JONATHAN H , MATHISEN ERIC , MOELLER DENNIS L , HERNANDEZ LUIS A , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially reqesting such access.
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公开(公告)号：BR9201915A
公开(公告)日：1993-01-12
申请号：BR9201915
申请日：1992-05-21
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN HENRY , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.
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公开(公告)号：CA2064163A1
公开(公告)日：1992-11-29
申请号：CA2064163
申请日：1992-03-26
Applicant: IBM
Inventor： FUOCO DANIEL P , HERNANDEZ LUIS A , MATHISEN ERIC , MOELLER DENNIS L , RAYMOND JONATHAN H , TASHAKORI ESMAEIL
Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.
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公开(公告)号：CA2130406A1
公开(公告)日：1995-05-18
申请号：CA2130406
申请日：1994-08-18
Applicant: IBM
Inventor： FUOCO DANIEL P , HERRING CHRISTOPHER M , KELLOGG MARK W , LENTO JORGE E
Abstract: ERROR CORRECTION CODE ON ADD-ON CARDS FOR WRITING PORTIONS OF DATA WORDS The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the addon memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.
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