公开(公告)号：CA1103368A

公开(公告)日：1981-06-16

申请号：CA301827

申请日：1978-04-24

Applicant: IBM

Inventor： HOFFMAN ROY L ,  KEMPKE WILLIAM G ,  MCCULLOUGH JOHN W ,  SOLTIS FRANK G ,  TURNER RICHARD T

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/18

Abstract: TASK HANDLING APPARATUS FOR A COMPUTER SYSTEM Task handling apparatus in a computer system is structured to be common to system control tasks, user tasks and I/O tasks. Although the task handling apparatus contains a task priority structure, all tasks are handled in the same manner, and there are no fixed interrupt levels for I/O tasks. There are N levels of priority, and N is variable. Each task is a server for a functional request. Task dispatching elements (TDE's) are enqueued in priority sequence on a task dispatching queue (TDQ). A task dispatcher functions to dispatch the highest priority TDE on the TDQ, if any, and to perform task switching. Intertask communication is accomplished by send message, send count, receive message and receive count mechansisms, and is coupled with task synchronization. Task synchronization is achieved by dequeueing and enqueueing TDE's on the TDQ. An active task becomes inactive dispatchable when a higher priority TDE is enqueued on the TDQ by send message or send count mechanisms. The active task becomes inactive waiting when a receive message or receive count is not satisfied. An inactive dispatchable task becomes the active task when it becomes the highest priority enqueued TDE on the TDQ by the receive message or receive count mechanisms. An inactive waiting task becomes either the active task or an inactive dispatchable task after being enqueued on the TDQ by the send message or send count mechanisms, depending upon whether it is the highest or other than the highest priority TDE on the TDQ.

公开(公告)号：CA1155964A

公开(公告)日：1983-10-25

申请号：CA365497

申请日：1980-11-26

Applicant: IBM

Inventor： HEISE NYLES N ,  HOFFMAN ROY L ,  KISS ISTVAN S ,  LEWIS DAVID O ,  PERTZBORN JAMES J ,  ROBINSON THOMAS S

IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18 ,  G06F13/00

Abstract: CONTROL APPARATUS FOR VIRTUAL ADDRESS TRANSLATION UNIT Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address in an I/O resolved address register reserved (unique) to the commanded I/O device connected to a shared I/O control unit and to repeat such an operation for each I/O device commanded by the CPU to do a data transfer and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into I/O resolved address registers shared for use by all of I/O devices whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit. RO9B0-001

公开(公告)号：CA1231460A

公开(公告)日：1988-01-12

申请号：CA488367

申请日：1985-08-08

Applicant: IBM

Inventor： AAKRE DAVID E ,  HOFFMAN ROY L ,  MOEN DAVID N ,  SCHMIERER QUENTIN G

IPC: G06F12/00 ,  G06F13/38

Abstract: REAL TIME DATA TRANSFORMATION AND TRANSMISSION OVERLEAP DEVICE A real time data transformation and transmission apparatus transforms data from a first data device and transfers the transformed data to a second data device which need not have a data transfer rate consistent with the first data device. Data from the first data device is divided into blocks and is compressed by a compression device and written into a buffer. A controller controls the buffer to transmit compressed data to the second data device as a function of the data receiving rate of the second data medium provided that the buffer contains a predetermined amount of data. While the buffer is transmitting data, the compressor is compressing further blocks of data which are being written to the buffer such that the predetermined amount of data is stored in the buffer upon completion of the buffer transmitting a block of data. This ensures that complete blocks of data are transmitted to the second data medium at the data receiving rate of the second data medium.

公开(公告)号：CA1173971A

公开(公告)日：1984-09-04

申请号：CA400639

申请日：1982-04-07

Applicant: IBM

Inventor： HOFFMAN ROY L ,  HOUDEK MERLE E ,  LOEN LARRY W ,  SOLTIS FRANK G

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/16 ,  G06F15/177

Abstract: Task dispatching for an asymmetric or symmetric multiprocessor system is provided where all the processors are dispatched from a single task dispatching queue. The workload, i.e. tasks, of the multiprocessor system is distributed to the available processors. Each processor includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system. RO980-005

公开(公告)号：FR2340583A1

公开(公告)日：1977-09-02

申请号：FR7639829

申请日：1976-12-30

Applicant: IBM

Inventor： HOFFMAN ROY L ,  KEMPKE WILLIAM G ,  SOLTIS FRANK G

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/455 ,  G06F9/06

Abstract: A special directly executable instruction, Fetch Instruction Operand Address (FIOA) is accessed in response to encountering a complex non-directly executable instruction. Execution of the FIOA instruction causes generation of control signals for address calculation of the operands in the non-directly executable instruction by the same I phase hardware used by other directly executable instructions.