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    2.
    发明专利
    未知

    公开(公告)号：FR2357000A1

    公开(公告)日：1978-01-27

    申请号：FR7716054

    申请日：1977-05-18

    Applicant: IBM

    Inventor： MICKA WILLIAM F ,  ROBINSON THOMAS S

    IPC: G06K9/20 ,  G06T3/40 ,  G06T3/60 ,  G06F7/06 ,  G06K9/00

    Abstract: 1533833 Storage arrangements INTERNATIONAL BUSINESS MACHINES CORP 15 June 1977 [30 June 1976] 25032/77 Heading G4A In apparatus for rotating by 90 degrees video data having 2048 bits per scan line, the data is deserialized and stored, parallel by byte, in successive row locations of a memory (40, Fig. 2, not shown) holding 2048 bytes in 8 rows, by incrementing address counter (41). Read out into registers (50-57) is effected column by column by incrementing the top 3 bits of the address counter for each state of the bottom 8 bits from which the rotated data may be read to an 8 by 8 storage array (60-67) so that corresponding bits of the 8 read out bytes are stored in the same column. Preferably two memories 118, 122 (Fig. 3) are used, one being read out whilst the other is loaded under the control of two counters (204, 206, Fig. 4, not shown) the first incremented normally for loading and the second having its top 3 bits incremented for each state of the bottom 8 bits for unloading, the top 3 bits being decoded to select to which if registers 150-157 the read out data is fed.

    ALLOCATING AND RESOLVING NEXT VIRTUAL PAGES FOR INPUT/OUTPUT
    4.
    发明专利
    ALLOCATING AND RESOLVING NEXT VIRTUAL PAGES FOR INPUT/OUTPUT 未知

    公开(公告)号：CA1137644A

    公开(公告)日：1982-12-14

    申请号：CA347544

    申请日：1980-03-12

    Applicant: IBM

    Inventor： HAMMER WILLIAM E ,  LEWIS DAVID O ,  REED JOHN W ,  ROBINSON THOMAS S ,  SLACK KEITH K

    IPC: G06F13/00

    Abstract: ALLOCATING AND RESOLVING NEXT VIRTUAL PAGES FOR INPUT/OUTPUT In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel virtual address information specifying the requested page and channel function information which indicates whether the requested page is to be transferred from secondary storage into main storage or merely allocated as a page in main storage. The channel forms the virtual address information and the channel function information into a page request function event which is stored in an I/O event stack in main storage for retrieval and processing by the CPU. RO9-78-035

    CONTROL APPARATUS FOR VIRTUAL ADDRESS TRANSLATION UNIT
    5.
    发明专利
    CONTROL APPARATUS FOR VIRTUAL ADDRESS TRANSLATION UNIT 未知

    公开(公告)号：CA1155964A

    公开(公告)日：1983-10-25

    申请号：CA365497

    申请日：1980-11-26

    Applicant: IBM

    Inventor： HEISE NYLES N ,  HOFFMAN ROY L ,  KISS ISTVAN S ,  LEWIS DAVID O ,  PERTZBORN JAMES J ,  ROBINSON THOMAS S

    IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18 ,  G06F13/00

    Abstract: CONTROL APPARATUS FOR VIRTUAL ADDRESS TRANSLATION UNIT Control apparatus is responsive to CPU I/O commands for initiating chained I/O data transfers to cause virtual address translation (VAT) apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address in an I/O resolved address register reserved (unique) to the commanded I/O device connected to a shared I/O control unit and to repeat such an operation for each I/O device commanded by the CPU to do a data transfer and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into I/O resolved address registers shared for use by all of I/O devices whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit. RO9B0-001

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