公开(公告)号：WO02059882A2

公开(公告)日：2002-08-01

申请号：PCT/EP0115254

申请日：2001-12-21

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： HSIAO RICHARD ,  ROBERTSON NEIL LESLIE ,  WEBB PATRICK RUSH

IPC: C25D7/00 ,  C23F4/00 ,  G11B5/31 ,  G11B5/17 ,  G11B5/187

CPC classification number: G11B5/3163 ,  G11B5/3116 ,  G11B5/313 ,  G11B5/3133 ,  Y10T29/4906

Abstract: Electroplated components of magnetic head (100, 150) are fabricated utilizing a seed layer (112, 160) that is susceptible to reactive ion etch removal techniques. The seed layer is comprised of tungsten or titanium is fabricated by sputter deposition, is electrically conductive wherein electroplated components, such as induction coil members (104) and magnetic poles (188), are effectively electroplated into photolithographically created photoresist trenches (108, 180) that are fabricated upon the seed layer. Following the electroplating, the photoresist layer is removed utilizing standard wet chemical process. Utilizing a fluorine species reactive ion etch process the seed layer is removed, significantly, the fluorine RIE process creates a gaseous tungsten or titanium fluoride compound removal product. The problem of seed layer redeposition along the sides of the electroplated components is overcome because the gaseous fluoride compound is not redeposited. Included is an enhanced two part seed layer (138), where the lower part (112) is tungsten, titanium or tantalum, the upper part (140) is composed of material that constitutes the component to be electroplated.

Abstract translation: 使用对反应离子蚀刻去除技术敏感的种子层（112,160）制造磁头（100,150）的电镀部件。 种子层由钨或钛组成，通过溅射沉积制造，是导电的，其中诸如感应线圈构件（104）和磁极（188）的电镀部件有效地电镀到光刻创建的光致抗蚀剂沟槽（108,180）中， 在种子层上制造。 在电镀之后，使用标准的湿法化学方法去除光致抗蚀剂层。 利用氟物质反应离子蚀刻工艺，除去种子层，显着地，氟RIE工艺产生气态钨或氟化钛化合物去除产物。 由于气态氟化物不再沉积，克服了沿着电镀部件侧面的种子层再沉积的问题。 包括增强的两部分种子层（138），其中下部（112）是钨，钛或钽，上部（140）由构成要被电镀的部件的材料构成。

公开(公告)号：WO02103687A3

公开(公告)日：2003-04-10

申请号：PCT/GB0202660

申请日：2002-05-29

Applicant: IBM ,  IBM UK

Inventor： HSIAO RICHARD ,  SANTINI HUGO ALBERTO EMILIO

IPC: G11B5/012 ,  G11B5/17 ,  G11B5/31

CPC classification number: G11B5/3163 ,  G11B5/012 ,  G11B5/17 ,  G11B5/3116 ,  G11B5/313 ,  Y10T29/49046

Abstract: The magnetic head of the present invention includes a narrow, high aspect ratio P2 pole tip and a high aspect ratio, fine pitch induction coil. Electroplating trenches (120, 128, 134) for the P2 pole tip (140) and the induction coil (170) are fabricated in a single RIE process step, and the P2 pole tip and the induction coil are thereafter separately plated up into their respective trenches to complete the fabrication of these structures. Briefly, following the fabrication of a P1 pole and the deposition of an insulation layer thereon, a patterned P2 pole tip seed layer (96). An etching mask pattern (112) includes both a P2 pole tip trench opening and an induction coil trench opening. Thereafter, in a single RIE etching step, the P2 pole tip trench is etched through the dielectric material down to the seed layer, and the induction coil trench is etched through the dielectric material down to the insulation layer. The P2 pole tip is then electroplated up into its trench. Thereafter, the induction coil is electroplated (170) up into the induction coil trench. A chemical mechanical polishing (CMP) step is next conducted to remove the excess induction coil material (168) and the RIE etching mask. Thereafter, a patterned insulation layer is deposited upon the induction coil, which is followed by the fabrication of a P2 pole yoke (192) thereupon.

Abstract translation: 本发明的磁头包括窄的高纵横比的P2极尖和高纵横比的细间距感应线圈。 在单个RIE工艺步骤中制造用于P2极尖端（140）和感应线圈（170）的电镀沟槽（120,128,134），然后将P2极尖端和感应线圈单独地电镀到它们各自的 沟槽来完成这些结构的制造。 简而言之，在P1极的制造和其上的绝缘层的沉积之后，形成图案化的P2极端种子层（96）。 蚀刻掩模图案（112）包括P2极尖沟槽开口和感应线圈沟槽开口。 此后，在单个RIE蚀刻步骤中，通过电介质材料将P2极尖沟槽蚀刻到种子层，并且感应线圈沟槽通过电介质材料被蚀刻到绝缘层。 然后将P2极尖端电镀到其沟槽中。 此后，将感应线圈电镀（170）到感应线圈沟槽中。 接下来进行化学机械抛光（CMP）步骤以去除多余的感应线圈材料（168）和RIE蚀刻掩模。 此后，在感应线圈上沉积图案化的绝缘层，然后在其上制造P2极轭（192）。

公开(公告)号：WO03021577A3

公开(公告)日：2003-09-25

申请号：PCT/EP0208826

申请日：2002-08-07

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： DINAN THOMAS ,  HSIAO RICHARD

IPC: G11B5/012 ,  G11B5/31

CPC classification number: G11B5/3163 ,  G11B5/012 ,  G11B5/3116 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/4906

Abstract: The magnetic head includes a P2 pole tip in which the P2 pole tip material is electroplated upon a sidewall of the P2 pole tip photolithographic trench (64). To accomplish this, a block of material (40) is deposited upon a write gap layer (34), such that a generally straight, vertical sidewall (44) of the block of material is disposed at the P2 pole tip location. Thereafter, an electroplating seed layer (50) is deposited upon the sidewall. A P2 pole tip trench (64) is photolithographically fabricated such that the sidewall (with its deposited seed layer) is exposed within the P2 pole tip trench. Thereafter, the P2 pole tip is formed by electroplating pole tip material (70) upon the seed layer and outward from the sidewall within the trench, The width of the P2 pole tip is (80) thus determined by the quantity of pole tip material (88) that is deposited upon the sidewall.

Abstract translation: 磁头包括P2极尖端，其中P2极端材料电镀在P2极端光刻沟槽（64）的侧壁上。 为了实现这一点，将一块材料（40）沉积在写间隙层（34）上，使得材料块的大致直的垂直侧壁（44）设置在P2极尖端位置处。 此后，电镀种子层（50）沉积在侧壁上。 P2极端沟槽（64）被光刻地制造成使得侧壁（其沉积的种子层）暴露在P2极尖端沟槽内。 此后，P2极端部通过在种子层上电镀极尖材料（70）并且在沟槽内从侧壁向外侧形成。因此，P2极尖端的宽度（80）由极尖材料的量 88），其沉积在侧壁上。

公开(公告)号：DE69115996T2

公开(公告)日：1996-07-11

申请号：DE69115996

申请日：1991-04-30

Applicant: IBM

Inventor： DAVIS CHARLES R ,  HSIAO RICHARD ,  LOOMIS JAMES R ,  PARK JAE M ,  REID JONATHAN D

IPC: H01R43/02 ,  B23K35/00 ,  B23K35/30 ,  H01R4/02 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46

Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.

公开(公告)号：DE69115996D1

公开(公告)日：1996-02-15

申请号：DE69115996

申请日：1991-04-30

Applicant: IBM

Inventor： DAVIS CHARLES R ,  HSIAO RICHARD ,  LOOMIS JAMES R ,  PARK JAE M ,  REID JONATHAN D

IPC: H01R43/02 ,  B23K35/00 ,  B23K35/30 ,  H01R4/02 ,  H05K3/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46

Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.