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公开(公告)号：JP2004214626A
公开(公告)日：2004-07-29
申请号：JP2003396313
申请日：2003-11-26
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： WILLIAM F LANDERS , SHAW THOMAS M , LLERA-HURLBURT DIANA , CROWDER SCOTT W , MCGAHAY VINCENT J , MALHOTRA SANDRA G , DAVIS CHARLES R , RONALD D GOLDBLATT , ENGEL BRETT H
IPC: H01L23/52 , H01L21/3205 , H01L21/822 , H01L23/544 , H01L27/04
CPC classification number: H01L23/585 , H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To obtain improved crack stopping and contaminant barriers for an IC chip. SOLUTION: On-chip overlapped crack end barrier structure is constituted. A conductive material in barrier structure design is used for forming the depth of several conductive layers, by wiring each barrier to a contact pad and a device pin and connecting a monitoring device to a chip. Upper surface deposit, consisting of a material such as polyimide, suppresses peeling off of layers. Other barriers may include structural characteristics for completely shielding moisture absorption and oxidation, as compared with typical crack stopping structure. Thereto, other barriers are constituted so as to give crack stop protection, to be electrically connected to a monitoring device and so as to test the capacitance/resistance of the barrier structure to show the complete states of the barriers to a user. A barrier destroyed by cracks or humidity absorption/oxidation shows deviation in the capacitance/resistance. COPYRIGHT: (C)2004,JPO&NCIPI
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2.发明专利
公开(公告)号：JP2003243401A
公开(公告)日：2003-08-29
申请号：JP2003019203
申请日：2003-01-28
Applicant: IBM
Inventor： DAVIS CHARLES R , HAWKEN DAVID L , JUNG DAE YOUNG , WILLIAM F LANDERS , QUESTAD DAVID L
IPC: H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532 , H01L23/58
Abstract: PROBLEM TO BE SOLVED: To manufacture a mesh-like reinforcing structure inhibiting peeling and cracking in a multilayer semiconductor structure using a low dielectric constant dielectric material and a copper-based metal wire. SOLUTION: A mesh-like interconnecting structure is provided with electrically conductive pads 45 that are interconnected by electrically conductive lines 37 and 38 at each wiring level, and each electrically conductive pad is connected with the adjacent pad at the next wiring level through a plurality of electrically conductive via holes. The electrically conductive pads, lines and via holes are manufactured in a normal BEOL device wiring level integration process. This mesh-like reinforcing structure can be manufactured in the periphery of the device like a chip or in the empty region of the device requiring a connection for inhibiting peeling. COPYRIGHT: (C)2003,JPO
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Patent Agency Ranking
公开(公告)号：JP2001284454A
公开(公告)日：2001-10-12
申请号：JP2001047144
申请日：2001-02-22
Applicant: IBM
Inventor： DAVIS CHARLES R , EDELSTEIN DANIEL CHARLES , HAY JOHN C , HEDRICK JEFFREY C , JAHNES CHRISTOPHER , MC GAHAY VINCENT , NYE HENRY A
IPC: H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532
Abstract: PROBLEM TO BE SOLVED: To improve a rigidity of a backend-of-line structure. SOLUTION: The damascene structure of interconnecting multi-level coppers on an integrated circuit chip includes several line conductors which are on the integrated circuit and are separated by dielectric materials having quite low dielectric constant and high elastic modulus. A second flat interconnection layer 18 on the first flat interconnection layer 14, consists of a dielectric film 26 having a higher elastic modulus than that of a dielectric material in the first flat interconnection layer 14, and an electrical conduction via 28 passing through the dielectric film 26. Electrical conduction vias 28 contact line conductors 22 selectively. A third flat interconnection layer 20 on the second flat interconnection layer 18, has several line conductors 22 which are isolated by dielectric materials and contact electrical conduction vias selectively.
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公开(公告)号：DE69115996D1
公开(公告)日：1996-02-15
申请号：DE69115996
申请日：1991-04-30
Applicant: IBM
Inventor： DAVIS CHARLES R , HSIAO RICHARD , LOOMIS JAMES R , PARK JAE M , REID JONATHAN D
Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
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公开(公告)号：DE10106161A1
公开(公告)日：2001-09-13
申请号：DE10106161
申请日：2001-02-10
Applicant: IBM
Inventor： DAVIS CHARLES R , EDELSTEIN DANIEL CHARLES , HAY JOHN C , HEDRICK JEFFREY C , JAHNES CHRISTOPHER , MC GAHAY VINCENT , NYE HENRY
IPC: H01L21/768 , H01L21/3205 , H01L23/52 , H01L23/522 , H01L23/532
Abstract: Planar layer for conductors, includes numerous connecting lines separated from each other by dielectric. This has relatively low: dielectric constant and modulus of elasticity. A planar, perforated dielectric film layer included, has a higher modulus of elasticity. One of the conductor- and the perforated layers, is located on an integrated circuit substrate, defining a first layer. The other conductor- and perforated layer is located on the first, such that perforations make selective contact with conductors of the conductor layer.
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公开(公告)号：DE69115996T2
公开(公告)日：1996-07-11
申请号：DE69115996
申请日：1991-04-30
Applicant: IBM
Inventor： DAVIS CHARLES R , HSIAO RICHARD , LOOMIS JAMES R , PARK JAE M , REID JONATHAN D
Abstract: A method is disclosed of simultaneously laminating circuitized dielectric layers to form a multilayer high performance circuit board and making interlevel electrical connections. The method selects two elements which will form a eutectic at one low temperature and will solidify to form an alloy which will only remelt at a second temperature higher than any required by any subsequent lamination. The joint is made using a transient liquid bonding technique and sufficient Au and Sn to result in a Au-Sn20wt% eutectic at the low temperature. Once solidified, the alloy formed remains solid throughout subsequent laminations. As a result, a composite, mulilayer, high performance circuit board is produced, electrically joined at selected lands by the solid alloy.
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公开(公告)号：CA2044573A1
公开(公告)日：1992-01-07
申请号：CA2044573
申请日：1991-06-13
Applicant: IBM
Inventor： DAVIS CHARLES R , GOLDBLATT RONALD D , PARK JAE M
IPC: B29C41/12 , B29K79/00 , B29L7/00 , B32B27/06 , B32B27/34 , C08G73/10 , C08J5/18 , C09D179/08 , H01B3/30 , H05K1/03 , B29C39/14 , B29C39/38 , B32B31/12 , H05K1/05
Abstract: A structure comprising a free-standing polyamic acid film substantially free of phthalic acids. A method of fabricating such a structure which comprises applying a polyamic acid solution to a substrate, partially or substantially completely removing the solvent from the polyamic acid solution by heating the same, removing the free-standing polyamic acid film which is free from phthalic acids, laminating the film to a substrate at elevated temperature and pressure and thermally curing the laminated, free-standing polyamic acid film to the corresponding polyimide. A structure comprising one or a plurality of such free-standing polyamic acid films with electrically conducting layers therebetween is also disclosed as is a method of fabricating such a structure. Further disclosed is the use of a thermoplastic polyimide adhesive precursor which permits 2nd level multilayer packaging applications and a method for forming such packaging.
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