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    EFFICIENT INTERFACE FOR THE MAIN STORE OF A DATA PROCESSING SYSTEM
    3.
    发明专利
    EFFICIENT INTERFACE FOR THE MAIN STORE OF A DATA PROCESSING SYSTEM 未知

    公开(公告)号：CA1299764C

    公开(公告)日：1992-04-28

    申请号：CA569055

    申请日：1988-06-09

    Applicant: IBM

    Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

    IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

    Abstract: FR 9 87 018 EFFICIENT INTERFACE FOR THE MAIN STORE OF A DATA PROCESSING SYSTEM The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended. (Figure 1)

    7.
    发明专利
    未知

    公开(公告)号：DE3782500T2

    公开(公告)日：1993-05-06

    申请号：DE3782500

    申请日：1987-12-23

    Applicant: IBM

    Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

    IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

    Abstract: The memory interface mechanism according to the invention is driven from the memory controller side. It comprises lines which are shared by the memory user devices 1 and 2 and lines which are specific to the memory user devices. The shared lines are the address and data bus lines 20,22, the byte select lines 24 the data and address clock lines 26 and 24 and the last operation line 30. The specific lines are request lines 11 and 12, address user indicator and data user indicator lines 15,17;16,18. A user initiates a memory operation by activating its request line, then it waits for the activation by the memory interface control circuit 5 for the activation of the address and data user indicator lines 15 and 17. The user controls the address and data transfer count and ends the transfer by activating the last operation line 30. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven, which allows to take fully advantage of the page mode facility of the memory. The memory operations may be pipelined since servicing a request from a user may be started before servicing the request from the the previous selected user is ended.

    8.
    发明专利
    未知

    公开(公告)号：DE3786080D1

    公开(公告)日：1993-07-08

    申请号：DE3786080

    申请日：1987-08-20

    Applicant: IBM

    Inventor： DEBIZE JEAN-CLAUDE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

    IPC: G06F12/04 ,  G06F13/28 ,  G06F13/40

    Abstract: The processor (14) initiates data transfer to or from a selected input-output device on a processor bus (18) by sending a receive or transmit command and the starting address and burst length allocated in memory to the input-output device, to the memory format adapter (10) on the data bus (22). For controlling the input-output device and the memory, the memory format adapter generates read-write controlsignals on a line (24) and byte select control signals and address signals on a respective bus (26,28) to the memory (16). The memory is organised in four-byte words and the data bus is two bytes wide so that the adapter includes alignment and control devices for determining the byte location within the memory words.

    9.
    发明专利
    未知

    公开(公告)号：DE3782500D1

    公开(公告)日：1992-12-10

    申请号：DE3782500

    申请日：1987-12-23

    Applicant: IBM

    Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

    IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

    Abstract: The interface mechanism provides one memory request line (11, 12) for each user device and which is activated by the user device when it requests an access to the memory to effect a memory read or write transfer. A last operation line (30), shared by the user devices, is activated by the user device when its memory transfer is complete. An address user indicator line (15,16) and a data user indicator line (17,18) are provided for each user device. An address clock line (26) and a data clock line (28) are shared by the user devices. A memory interface controller (5) responds to the status of memory request lines to select a request from a user device, and to activate the address user and data user indicator lines of the selected device during the periods when the selected device may use the address, data bus. In addition, the controller sends clock pulses for timing transfer of the address and data signals on the respective bus. User interface controls (3-1, 3-2) respond to the controller clock pulses.

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