公开(公告)号：CA2280125A1

公开(公告)日：2000-03-29

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

公开(公告)号：CA2280125C

公开(公告)日：2003-01-07

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: The invention relates to memory access and provided non-uniform memory acces s (NUMA) data processing system includes a node interconnect to which at least a firs t processing node and a second processing node are coupled. The first and the second processing node s each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnec t and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the reques t transaction should be processed at the second processing node.

公开(公告)号：BR9903228A

公开(公告)日：2000-10-03

申请号：BR9903228

申请日：1999-06-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2279138A1

公开(公告)日：2000-02-17

申请号：CA2279138

申请日：1999-07-29

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  CARPENTER GARY DALE ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F15/16 ,  G06F12/08 ,  G06F12/02 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

公开(公告)号：MY124353A

公开(公告)日：2006-06-30

申请号：MYPI9903692

申请日：1999-08-26

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR

IPC: G06F13/00 ,  G06F15/163 ,  G06F12/08

Abstract: A NON-UNIFORM MEMORY ACCESS (NUMA) DATA PROCESSING SYSTEM (8) INCLUDES A NODE AND SECOND INTERCONNECT (22) TO WHICH AT LEAST A FIRST PROCESSING NODE ARE COUPLED. THE FIRST AND THE SECOND PROCESSING NODES EACH INCLUDES A LOCAL INTERCONNECT (16), A PROCESSOR (12A-12D) COUPLED TO THE LOCAL INTERCONNECT, A SYSTEM MEMORY (18) COUPLED TO THE LOCAL INTERCONNECT, AND A NODE CONTROLLER (20) INTERPOSED BETWEEN THE LOCAL INTERCONNECT AND THE NODE INTERCONNECT. IN ORDER TO REDUCE COMMUNICATION LATENCY, THE NODE CONTROLLER OF THE FIRST PROCESSING NODE SPECULATIVELY TRANSMITS REQUEST TRANSACTIONS RECEIVED FROM THE LOCAL INTERCONNECT OF THE FIRST PROCESSOR NODE TO THE SECOND PROCESSING NODE VIA THE NODE INTERCONNECT.IN ONE EMBODIMENT, THE NODE CONTROLLER OF THE FIRST PROCESSING NODE SUBSEQUENTLY TRANSMITS A STATUS SIGNAL TO THE NODE CONTROLLER OF THE SECOND PROCESSING NODE IN ORDER TO INDICATE HOW THE REQUEST TRANSACTION SHOULD BE PROCESSED AT THE SECOND PROCESSING NODE.FIGURE 1

公开(公告)号：CA2279138C

公开(公告)日：2006-03-21

申请号：CA2279138

申请日：1999-07-29

Applicant: IBM

Inventor： IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  GLASCO DAVID BRIAN

IPC: G06F12/02 ,  G06F15/16 ,  G06F12/08

Abstract: A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remot e processing node. In response to receipt of the communication transaction by the remote processin g node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.