公开(公告)号：JP2002033395A

公开(公告)日：2002-01-31

申请号：JP2001160150

申请日：2001-05-29

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  ROBERT A GROVES ,  JEFFREY JOHNSON ,  SESHADORI SUBANA ,  VOLANT RICHARD P

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

Abstract: PROBLEM TO BE SOLVED: To improve the high-frequency performance of transistor design, and a manufacturing yield by combining processes from various techniques for eliminating and reducing the source of parasitic capacity. SOLUTION: Collector, base, and emitter regions are formed on a substrate, a second substrate is mounted, an original substrate is completely or partially removed, a non-active collector region is removed or is set to a semi-insulator, and wiring and contact are performed from the original back surface of a chip. A dielectric material used in a manufacturing process is removed, thus further reducing electrostatic capacity. A high-frequency transistor is jointed to a CMOS chip or a wafer, thus forming a BICMOS chip.