公开(公告)号：JP2002020891A

公开(公告)日：2002-01-23

申请号：JP2001127259

申请日：2001-04-25

Applicant: IBM

Inventor： VOLANT RICHARD P ,  PETER S LOCKE ,  PETRARCA KEVIN S ,  DAVID M ROCKWELL ,  SESHADORI SUBANA

IPC: C25D7/12 ,  C25D5/02 ,  C25D5/48 ,  H01L21/28 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide an electric plating method of a metal structure in a feature formed in a substrate. SOLUTION: A liner material 22 is adhered to an upper surface of the substrate and a bottom surface and a side wall of the feature 21. Next, a seed layer 23 is adhered onto the liner by the CVD. The seed layer is selectively removed from the upper surface of the substrate so that the seed layer is left behind only on the bottom surface of the feature. The metal is electrically plated by using this part of the seed layer so that the metal fills the feature. The upper surface is not electrically plated because the seed layer is removed from the upper surface of the substrate.

公开(公告)号：JP2002033395A

公开(公告)日：2002-01-31

申请号：JP2001160150

申请日：2001-05-29

Applicant: IBM

Inventor： GREGORY G FREEMAN ,  ROBERT A GROVES ,  JEFFREY JOHNSON ,  SESHADORI SUBANA ,  VOLANT RICHARD P

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082

Abstract: PROBLEM TO BE SOLVED: To improve the high-frequency performance of transistor design, and a manufacturing yield by combining processes from various techniques for eliminating and reducing the source of parasitic capacity. SOLUTION: Collector, base, and emitter regions are formed on a substrate, a second substrate is mounted, an original substrate is completely or partially removed, a non-active collector region is removed or is set to a semi-insulator, and wiring and contact are performed from the original back surface of a chip. A dielectric material used in a manufacturing process is removed, thus further reducing electrostatic capacity. A high-frequency transistor is jointed to a CMOS chip or a wafer, thus forming a BICMOS chip.