公开(公告)号：US3740730A

公开(公告)日：1973-06-19

申请号：US3740730D

申请日：1971-06-30

Applicant: IBM

Inventor： HO I ,  JEN T

IPC: G11C8/10 ,  G11C11/414 ,  G11C11/415 ,  H03K3/35 ,  H03K17/00 ,  H03K17/62 ,  H03K17/73 ,  G11C7/00

CPC classification number: G11C11/415 ,  G11C8/10 ,  G11C11/414 ,  H03K3/35 ,  H03K17/6221 ,  H03K17/73 ,  H03K2217/0036

Abstract: A monolithic memory comprising an array of semiconductor storage cells and a plurality of decoders for accessing information to the storage cells during a given duty cycle. Reduced power consumption is achieved by the application of addressing signals to the decoder input lines for a given time period less than the accessing duty cycle in order to attain full duty cycle activating signals on the decoder output lines for accessing the memory array, and also by virtue of the selected address input lines associated with a selected decoder not drawing current during the given time period.

Abstract translation: 一种单片存储器，包括半导体存储单元阵列和用于在给定占空比期间向存储单元访问信息的多个解码器。 通过在小于访问占空比的给定时间周期内对解码器输入线应用寻址信号来实现降低的功耗，以便在解码器输出线上获得用于访问存储器阵列的全占空比激活信号，并且还通过 所选择的地址输入线与所选择的解码器相关联，在给定时间段期间不绘制电流。

公开(公告)号：US3806738A

公开(公告)日：1974-04-23

申请号：US31982272

申请日：1972-12-29

Applicant: IBM

Inventor： CHIN W ,  JEN T

IPC: H03F3/21 ,  H03F3/20 ,  H03F3/213 ,  H03F3/30 ,  H03K5/02 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/094 ,  H03K4/08

CPC classification number: H03K19/01714 ,  H03K5/023

Abstract: An integrated circuit FET push-pull driver includes a first FET boot-strap circuit for charging the driver output node to a value below the driver supply voltage. A second FET boot-strap circuit adds additional charge to the output node to drive the output node to the supply voltage. An FET clamping circuit functions to prevent the additional charge from leaking off through the first boot-strap circuit.

Abstract translation: 集成电路FET推挽驱动器包括用于将驱动器输出节点充电到低于驱动器电源电压的值的第一FET引导电路。 第二个FET引导电路为输出节点添加额外的电荷，以将输出节点驱动到电源电压。 FET钳位电路用于防止额外的电荷通过第一引导电路泄漏。

公开(公告)号：US3821781A

公开(公告)日：1974-06-28

申请号：US30296272

申请日：1972-11-01

Applicant: IBM

Inventor： CHANG C ,  JEN T

IPC: H01L21/331 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/73 ,  H01L29/78 ,  H01L19/00

CPC classification number: H01L27/0927 ,  H01L21/823842 ,  H01L29/00 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/122

Abstract: AN INSULATING GATE COMPLEMENTARY FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT USES SILICON AS THE GATE ELECTRODE. THE GATES OF BOTH N- AND P- CHANNEL TRANSISTORS ARE DOPED WITH P TYPE IMPURITIES, THEREBY BALANCING THE VOLTAGE THRESHOLD CHARACTERISTICS OF THE TRANSISTORS. THE GATE INSULATOR IS DUAL NITRIDE-OXIDE TYPE, WHICH, IN COMBINATION WITH THE P-TYPE GATES, RESULTS IN A HIGH SURFACE-STATE CHARGE DENSITY, AND REQUIRES PARTICULAR DOPING VALUES FOR THE CHANNELS OF THE COMPLEMENTARY TRANSISTORS.

公开(公告)号：US3796928A

公开(公告)日：1974-03-12

申请号：US3796928D

申请日：1971-11-03

Applicant: IBM

Inventor： DOO V ,  HO I ,  JEN T

IPC: G11C27/04 ,  G11C19/18 ,  H01L21/00 ,  H01L21/33 ,  H01L21/339 ,  H01L27/105 ,  H01L29/70 ,  H01L29/762 ,  H01L19/00

CPC classification number: H01L27/1055 ,  G11C19/186 ,  H01L21/00

Abstract: A semiconductor bucket brigade shift register having a plurality of cells, each cell embodying a transistor and a large capacitance element coupled across the base and the collector contacts of the transistor. Each cell, includes a first layer of insulating material bonded to the surface of the semiconductor body, a second layer of polycrystalline silicon overlying the first layer, a third layer of insulating material over the second layer, emitter, base, and collector contacts to the body of semiconductor material extending through the first, second, and third layers and insulated from the second layer, an electrical connection between the base contact and the second layer of polycrystalline material, and a relatively large surface area of a conductive layer in contact with the collector contact overlying at least in part the second layer.

公开(公告)号：CA929235A

公开(公告)日：1973-06-26

申请号：CA109046

申请日：1971-03-30

Applicant: IBM

Inventor： JEN T ,  HO I ,  HOWELL P

IPC: G11C19/18 ,  G11C19/28

Abstract: 1345604 Semi-conductor data storage cell INTERNATIONAL BUSINESS MACHINES CORP 27 May 1971 [30 June 1970] 17441/71 Heading H3T [Also in Division G4] A capacitor storage cell C28, C33, T44, T46 has its stored data refreshed or maintained by a transistor 50 cross-coupled with T46 (Fig. 1). C28 is charged by a pulse 16 (Fig. 1A) at terminal 14 via R22, D24 and line 26, and discharged or not by T44 if the data input 10 is high or low respectively, when a negative pulse 56 occurs at T44 emitter 30; then C33 is charged by pulse 32 at 30 via R36, D38 and discharged or not by T46 when a negative pulse 52 occurs at T46 emitter 14 depending upon the stored voltage on C28. To regenerate the information stored to allow for leakage, a similar cycle of pulses is applied at times t 5 -t 8 but instead of T44 discharging C28 in dependence on the input, T50 is biased by a pulse 50 at 58 to discharge C28 or not according to the already stored level on C33. The transistor 50 may be replaced by a cross-coupled pair (T128, 130, Fig. 2, not shown) and in this case stored, information is maintained merely by a constantly applied negative level - V at their commoned emitters (134). A shift register (Fig. 3, not shown) has a plurality of these cells (156-m) in each row (150-n).