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公开(公告)号：US3786445A
公开(公告)日：1974-01-15
申请号：US3786445D
申请日：1972-07-03
Applicant: IBM
CPC classification number: H01F10/06 , G11C19/085 , G11C19/0866
Abstract: A magnetic bubble device and its associated read, write, propagation, sensing, addressing, driving, timing and control elements are combined in a unitary magnetic sheet-semiconductor structure.
Abstract translation: 磁性气体装置及其相关的读，写，传播，感测，寻址，驱动，定时和控制元件组合在一体的磁性薄片半导体结构中。
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公开(公告)号：US3842414A
公开(公告)日：1974-10-15
申请号：US37100473
申请日：1973-06-18
Applicant: IBM
CPC classification number: H03M7/12
Abstract: Apparatus for encoding multi-digit binary-coded-decimal numbers of a predetermined quantity of bits, for example, of at least two decimal digits, into a re-expressed lower number of bits, the binary-coded-decimal number being expressed in the form (abcd) (efgh). An encoder selects a set from a class of sets of bit symbols with each set corresponding to a respective combination of the bits in the most significant position, (a) and (e), of each of the four-bit groups representing the respective digits of the binary-coded-decimal number to be encoded. The selected set is the set which corresponds to the respective combination and the encoder determines certain of the bits of the multi-digit binary-coded-decimal number to be encoded and leaves undetermined the remaining bits of the number. The encoder is connected to register means having a plurality of bit positions which are equal to the quantity of bits less than the predetermined quantity, and stores not only the determined bit symbols but also the undetermined other bits of the multi-digit binary-codeddecimal number.
Abstract translation: 用于将预定数量的位（例如至少两个十进制数字）的多位二进制编码十进制数编码为重新表示的较低位数的装置，二进制编码十进制数表示在 形式（abcd）（efgh）。 编码器从一组比特符号集合中选择一组，其中每个集合对应于表示相应数字的四比特组中的每一个的最高有效位置（a）和（e）中的比特的相应组合） 要编码的二进制编码十进制数。 所选集是对应于相应组合的集合，并且编码器确定要编码的多位二进制编码十进制数的某些位，并且不确定该数的剩余位。 编码器连接到具有等于小于预定量的位数的多个比特位置的寄存器装置，并且不仅存储所确定的比特符号，而且存储多位二进制编码的码元的未确定的其他比特， 十进制数。
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公开(公告)号：US3796928A
公开(公告)日：1974-03-12
申请号：US3796928D
申请日：1971-11-03
Applicant: IBM
IPC: G11C27/04 , G11C19/18 , H01L21/00 , H01L21/33 , H01L21/339 , H01L27/105 , H01L29/70 , H01L29/762 , H01L19/00
CPC classification number: H01L27/1055 , G11C19/186 , H01L21/00
Abstract: A semiconductor bucket brigade shift register having a plurality of cells, each cell embodying a transistor and a large capacitance element coupled across the base and the collector contacts of the transistor. Each cell, includes a first layer of insulating material bonded to the surface of the semiconductor body, a second layer of polycrystalline silicon overlying the first layer, a third layer of insulating material over the second layer, emitter, base, and collector contacts to the body of semiconductor material extending through the first, second, and third layers and insulated from the second layer, an electrical connection between the base contact and the second layer of polycrystalline material, and a relatively large surface area of a conductive layer in contact with the collector contact overlying at least in part the second layer.
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4.发明授权Dynamically ordered bidirectional shift register having charge coupled devices 失效具有充电耦合器件的动态双向移位寄存器
公开(公告)号：US3789247A
公开(公告)日：1974-01-29
申请号：US3789247D
申请日：1972-07-03
Applicant: IBM
Inventor： BEAUSOLEIL W , HO I , YU H
IPC: G11C27/04 , G06F3/00 , G06F12/00 , G11C19/28 , H01L21/339 , H01L27/105 , H01L29/762 , H01L11/14
CPC classification number: G06F3/007 , G11C19/285 , G11C19/287 , H01L27/1057
Abstract: The specification describes charge coupled devices in a bidirectional shift register and having a dynamic ordering capability. Charge coupled devices are shown in a semiconductor structure with FET amplifying circuits, uniquely adapted for bidirectional operation by means of a circuit which changes the order of occurrence of the clocking pulses. The density of charge coupled devices is preserved together with improved access time resulting from bidirectional operation and dynamic ordering.
Abstract translation: 本说明书描述了双向移位寄存器中的电荷耦合器件，并具有动态排序能力。 电荷耦合器件以具有FET放大电路的半导体结构示出，其独特地适用于通过改变时钟脉冲的发生次序的电路进行双向操作。 电荷耦合器件的密度与由双向操作和动态排序产生的改进的访问时间保持在一起。
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公开(公告)号：US3784976A
公开(公告)日：1974-01-08
申请号：US3784976D
申请日：1972-04-10
Applicant: IBM
Inventor： HO I
CPC classification number: G06F11/10 , G11C17/08 , Y10S148/037 , Y10S148/085
Abstract: An error detection system of n inputs is adaptable for fabrication in large scale integrated circuit form. An integrated circuit logic array provides a parity check in response to digital signals received via X and Y decoders. Reduction in the number of array cells and the X and Y driving decoder circuits is obtained by interconnecting even parity subgroups and odd parity subgroups of lines from the X and Y decoders to provide even master parity lines and odd master parity lines. A logic array having less than 2n operative cells compares the signals on the master lines and generates an error parity signal. The improvement described herein specifically separates the decoder driver circuits into independent subgroups, each having their own array comparators for handling a large number of inputs.
Abstract translation: n个输入的误差检测系统适用于大规模集成电路形式的制造。 集成电路逻辑阵列响应于经由X和Y解码器接收的数字信号提供奇偶校验。 通过将来自X和Y解码器的偶校验子组和奇校验子组相互连接来提供阵列单元数量和X和Y驱动解码器电路的减少，以提供偶校验奇偶校验线和奇数主奇偶校验线。 具有小于2n个操作单元的逻辑阵列比较主线上的信号并产生误差奇偶校验信号。 本文所述的改进特别将解码器驱动器电路分离成独立的子组，每个子组具有用于处理大量输入的它们自己的阵列比较器。
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Patent Agency Ranking
公开(公告)号：US3816728A
公开(公告)日：1974-06-11
申请号：US31526872
申请日：1972-12-14
Applicant: IBM
CPC classification number: G06F11/104
Abstract: A modulo 9 residue generating and checking circuit for checking the accuracy of decimal addition operations in digital computers and other data processing equipment. A set of data words each representing a number to be added is transmitted to a multinumber adder which adds the words and provides a smaller set of words as a subtotal sum. The bits of the subtotal words are then divided into two groups. Each group of bits is fed to a respective modulo 9 residue generator which calculates the modulo 9 residue of the group. The two resulting residues are then fed to a third modulo 9 residue generator which calculates the modulo 9 residue of the sum of the two residues, thereby providing the modulo 9 residue of the sum of the original set of data words. This result may then be compared in the conventional manner with the modulo 9 residue of the sum resulting from the addition operation to be checked.
Abstract translation: 一种用于检查数字计算机和其他数据处理设备中十进制加法运算精度的模9残差生成和检查电路。 将表示要添加的数字的一组数据字发送给多位加法器，该多位加法器相加字并提供较小的一组单词作为小计和。 然后将小计字的位分成两组。 每组比特被馈送到相应的模9残差生成器，其计算组的模9残差。 然后将得到的两个残差送入第三个模9残差生成器，该第三个模9残差生成器计算两个残差之和的模9个残差，从而提供原始数据集合的和的模9残差。 然后将该结果以常规方式与由待检查的相加操作产生的总和的模9残差进行比较。
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公开(公告)号：US3781793A
公开(公告)日：1973-12-25
申请号：US3781793D
申请日：1972-04-10
Applicant: IBM
CPC classification number: G06F11/10
Abstract: An error detection system of n inputs is adaptable for fabrication in large scale integrated circuit form. An integrated circuit logic array provides a parity check in response to digital signals received via X and Y decoders. Reduction in the number of array cells and the X and Y driving decoder circuits is obtained by interconnecting even parity subgroups and odd parity subgroups of lines from the X and Y decoders to provide even master parity lines and odd master parity lines. A logic array having less than 2n operative cells compares the signals on the master lines and generates an error parity signal.
Abstract translation: n个输入的误差检测系统适用于大规模集成电路形式的制造。 集成电路逻辑阵列响应于经由X和Y解码器接收的数字信号提供奇偶校验。 通过将来自X和Y解码器的偶校验子组和奇校验子组相互连接来提供阵列单元数量和X和Y驱动解码器电路的减少，以提供偶校验奇偶校验线和奇数主奇偶校验线。 具有小于2n个操作单元的逻辑阵列比较主线上的信号并产生误差奇偶校验信号。
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公开(公告)号：US3740730A
公开(公告)日：1973-06-19
申请号：US3740730D
申请日：1971-06-30
Applicant: IBM
IPC: G11C8/10 , G11C11/414 , G11C11/415 , H03K3/35 , H03K17/00 , H03K17/62 , H03K17/73 , G11C7/00
CPC classification number: G11C11/415 , G11C8/10 , G11C11/414 , H03K3/35 , H03K17/6221 , H03K17/73 , H03K2217/0036
Abstract: A monolithic memory comprising an array of semiconductor storage cells and a plurality of decoders for accessing information to the storage cells during a given duty cycle. Reduced power consumption is achieved by the application of addressing signals to the decoder input lines for a given time period less than the accessing duty cycle in order to attain full duty cycle activating signals on the decoder output lines for accessing the memory array, and also by virtue of the selected address input lines associated with a selected decoder not drawing current during the given time period.
Abstract translation: 一种单片存储器，包括半导体存储单元阵列和用于在给定占空比期间向存储单元访问信息的多个解码器。 通过在小于访问占空比的给定时间周期内对解码器输入线应用寻址信号来实现降低的功耗，以便在解码器输出线上获得用于访问存储器阵列的全占空比激活信号，并且还通过 所选择的地址输入线与所选择的解码器相关联，在给定时间段期间不绘制电流。
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公开(公告)号：US3723715A
公开(公告)日：1973-03-27
申请号：US3723715D
申请日：1971-08-25
Applicant: IBM
Abstract: A fast adder for adding more than three words, the correspondingly weighted bits of which are applied to respective bit column adders. The column adders simultaneously produce respective sum and carry result bits of overlapping positional significance or weight. The maximum number of result bits having the same weight is determined by the quantity of words to be added at the same time (which establishes the number of bits in each bit column). In the disclosed embodiment, seven words are added at a given time and no more than three of the generated result bits have the same weight. In effect, the seven operand words are reduced to a subtotal of three result operand words in one computational cycle irrespective of the bit length of the words being added. The subtotal operands are reduced to a final sum by application to conventional carry save and carry lookahead adders. Equal weighted wire-ORing and matrix memory techniques are employed in the respective column adders to conserve required computational hardware and to facilitate large scale circuit integration.
Abstract translation: 一个用于添加三个以上字的快速加法器，相应的加权位应用于相应的位列加法器。 列加法器同时产生相应的和并携带具有重叠位置重要性或重量的结果位。 具有相同权重的结果比特的最大数目由同时添加的单词量确定（确定每个比特列中的比特数）。 在所公开的实施例中，在给定时间添加七个字，并且不超过三个生成的结果位具有相同的权重。 实际上，在一个计算周期内，七个操作数字减少到三个结果操作数字的小计，而不管被添加的字的位长度。 小计操作数通过应用于常规携带保存并携带预先加法器而减少到最终总和。 在各列加法器中采用等加权线性和矩阵存储技术来节省所需的计算硬件并促进大规模电路集成。
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公开(公告)号：US3820086A
公开(公告)日：1974-06-25
申请号：US24907672
申请日：1972-05-01
Applicant: IBM
CPC classification number: G11C7/20 , G11C11/4116 , G11C17/08 , G11C17/12 , H03K3/286 , H03K3/356008 , H03K3/35606
Abstract: The disclosures describes a transistor storage cell operable both as a random access read/write memory cell or as a read only memory cell. The memory cell structure includes a bistable circuit adapted to be set into one of two stable conditions and an imbalancing means for providing structural asymmetry. The memory cell is operable either as a read/write cell or, by accessing the cell through the imbalancing means, the latent image provided by the structural asymmetry of the cell is read out without affecting the information contained in the cell from the read/write mode of operation.
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