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    POWER DRIVING CIRCUIT
    2.
    发明专利
    POWER DRIVING CIRCUIT 未知

    公开(公告)号：DE3269224D1

    公开(公告)日：1986-03-27

    申请号：DE3269224

    申请日：1982-11-05

    Applicant: IBM

    Inventor： JENKINS MICHAEL OWEN

    IPC: H03F1/02 ,  H03F3/20 ,  H03F3/217 ,  H03F3/72

    Abstract: A dual operating mode switching power driving circuit arrangement comprises an amplifying circuit (18) of conventional form which is operated substantially as a Class A feedback amplifier in a servosystem "following" mode and is switched to operate as a Class D amplifier in the "seeking" mode under program control calling for the latter mode and reswitched to the "following" mode only at the succeeding transition of the Glass D waveform whereby transients are avoided. For operating in Class D mode, the Class A feedback loop is opened and the amplifier circuit is arranged so that the input wave now overdrives the input circuit and drives the output circuit between +/- values of the energy potential, whereby the efficiency is very high. A single electronic switching circuit (16) and logical circuitry (40) connected thereto are arranged to deliver selectively a driving control signal from such input terminals to the input circuit of a conventional amplifier for operating it in the Class A linear second order negative feedback loop arrangement and to deliver an overdriving feedback signal from the output terminal of the amplifier, the duty cycle of which responds to load device current passing a sensing device for operating the amplifier in the Class D mode. Preferably, the application of control signals is under program control along with such control over the operation of the load device (20).

    3.
    发明专利
    未知

    公开(公告)号：DE69620497T2

    公开(公告)日：2003-12-18

    申请号：DE69620497

    申请日：1996-01-25

    Applicant: IBM

    Inventor： ANNAPAREDDY NARASIMHAREDDY L ,  FINNEY DAMON W ,  JENKINS MICHAEL OWEN ,  KESSLER LARRY BURTON ,  LANG DONALD JOHN ,  MORA DAVID NICK ,  LIANG SONG CHYAU ,  PLOMGREN DAVID ARTHUR ,  URBISCI PETER P ,  WALLS ANDREW D

    IPC: G06F15/173 ,  G06F1/18 ,  G06F13/40

    Abstract: An interconnection network is proposed which preferably comprises a pair of backplanes 10, 12 for receiving X pluggable node cards. The pair of backplanes include x backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group preferably includes X/2 connectors. A first backplane 10 includes first permanent wiring 24, 26, 28, 30, 32, 34 which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane 12 includes second permanent wiring 42, 44, 46, 48, 50, 52 which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

    4.
    发明专利
    未知

    公开(公告)号：DE69620497D1

    公开(公告)日：2002-05-16

    申请号：DE69620497

    申请日：1996-01-25

    Applicant: IBM

    Inventor： ANNAPAREDDY NARASIMHAREDDY L ,  FINNEY DAMON W ,  JENKINS MICHAEL OWEN ,  KESSLER LARRY BURTON ,  LANG DONALD JOHN ,  MORA DAVID NICK ,  LIANG SONG CHYAU ,  PLOMGREN DAVID ARTHUR ,  URBISCI PETER P ,  WALLS ANDREW D

    IPC: G06F15/173 ,  G06F1/18 ,  G06F13/40

    Abstract: An interconnection network is proposed which preferably comprises a pair of backplanes 10, 12 for receiving X pluggable node cards. The pair of backplanes include x backplane connector groups, each backplane connector group adapted to receive mating connectors from a pluggable node card. Each backplane connector group preferably includes X/2 connectors. A first backplane 10 includes first permanent wiring 24, 26, 28, 30, 32, 34 which interconnects a first subset of pairs of connectors between backplane connector groups. A second backplane 12 includes second permanent wiring 42, 44, 46, 48, 50, 52 which interconnects a second subset of pairs of connectors between backplane connector groups. The first permanent wiring and second permanent wiring connect complementary subsets of pairs of the connectors. A plurality of node cards, each including a card connector group, pluggably mate with the backplane connector groups. Each node card further includes a frontal connector that is adapted to receive a cable interconnection. Each node card includes a processor and a switch module which simultaneously connects the processor to at least plural connectors of a backplane connector group.

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