Phase-change memory with no drift

    公开(公告)号:GB2605325A

    公开(公告)日:2022-09-28

    申请号:GB202208666

    申请日:2020-11-20

    Applicant: IBM

    Abstract: A bottom electrode(110) is deposited on top of a substrate(105). A dielectric material layer(115) is deposited on top of the bottom electrode(110). A hole is created in the dielectric material layer(115). A lift off layer(116) is spun on and baked on the dielectric material layer(115). A photoresist layer(117) is spun on and baked on the lift off layer(116). UV lithography is performed to create an opening above the hole in the dielectric material layer(115). An Ag layer(120) is deposited on top of the remaining patterned dielectric material layer and the photoresist layer(117). A Germanium Antimony Telluride (GST) layer(130) is deposited on top of the Ag layer(120). A top electrode(140) is deposited on top of the GST layer(130). The Ag layer(120), the GST layer(130) and the top electrode(140) located on top of the photoresist layer(117) along with the photoresist layer(117) and the lift off layer(116) are removed.

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