公开(公告)号：GB2605325A

公开(公告)日：2022-09-28

申请号：GB202208666

申请日：2020-11-20

Applicant: IBM

Inventor： NING LI ,  JOEL DE SOUZA ,  STEPHEN BEDELL ,  DEVENDRA SADANA

IPC: H01L45/00

Abstract: A bottom electrode(110) is deposited on top of a substrate(105). A dielectric material layer(115) is deposited on top of the bottom electrode(110). A hole is created in the dielectric material layer(115). A lift off layer(116) is spun on and baked on the dielectric material layer(115). A photoresist layer(117) is spun on and baked on the lift off layer(116). UV lithography is performed to create an opening above the hole in the dielectric material layer(115). An Ag layer(120) is deposited on top of the remaining patterned dielectric material layer and the photoresist layer(117). A Germanium Antimony Telluride (GST) layer(130) is deposited on top of the Ag layer(120). A top electrode(140) is deposited on top of the GST layer(130). The Ag layer(120), the GST layer(130) and the top electrode(140) located on top of the photoresist layer(117) along with the photoresist layer(117) and the lift off layer(116) are removed.

公开(公告)号：GB2574776B

公开(公告)日：2022-03-30

申请号：GB201914035

申请日：2018-02-21

Applicant: IBM

Inventor： YUN SEOG LEE ,  DEVENDRA SADANA ,  SOUZA DE

IPC: H01M10/058 ,  H01M4/64 ,  H01M10/0525

Abstract: A solid-state lithium-based battery is provided in which the formation of lithium islands (i.e., lumps) during a charging/recharging cycle is reduced, or even eliminated. Reduction or elimination of lithium islands (i.e., lumps) can be provided by forming a lithium nucleation enhancement liner between a lithium-based solid-state electrolyte layer and a top electrode of a solid-state lithium based battery.

公开(公告)号：GB2580827B

公开(公告)日：2022-02-23

申请号：GB202004615

申请日：2018-09-21

Applicant: IBM

Inventor： JOEL PEREIRA DE SOUZA ,  NING LI ,  YAO YAO ,  DEVENDRA SADANA ,  YUN SEOG LEE

IPC: H01L33/00

Abstract: A semiconductor device is formed using an n-type layer of Zinc Oxide, a p-type layer formed of a narrow bandgap material. The narrow bandgap material uses a group 3A element and a group 5A element. A junction is formed between the n-type layer and the p-type layer, the junction being operable as a heterojunction diode having a rectifying property at a temperature range, the temperature range having a high limit at room temperature.

公开(公告)号：GB2538594A

公开(公告)日：2016-11-23

申请号：GB201604088

申请日：2016-03-10

Applicant: IBM

Inventor： NING LI ,  DEVENDRA SADANA ,  EFFENDI LEOBANDUNG

IPC: H01L21/8258 ,  B82Y20/00 ,  G02B6/12 ,  G02B6/13 ,  H01L21/70 ,  H01L27/04 ,  H01L27/15 ,  H01L31/0304 ,  H01L31/18 ,  H01S5/026

Abstract: A method of forming a III-V optoelectronic device 115 and a Si CMOS device on a single chip may include forming a silicon substrate in both a first and second region 101, 103 of a single chip; forming a germanium layer 106 above the substrate in at least the first region; forming the optoelectronic device 115 on the germanium layer in the first region, and forming the silicon device 112 on a silicon layer in the second region 103. The optoelectronic device includes a bottom cladding layer 116, an active region 118 which is adjacent a waveguide 114 and a top cladding layer 117, each layer formed consecutively upon the germanium layer. In one embodiment, a semiconductor layer (206; Fig. 10) is formed on the substrate in first and second regions; a first insulator layer (204; Fig. 10) is formed over the semiconductor layer; a waveguide (214; Fig. 10) is formed over the first insulator layer; and a second insulator layer (208; Fig. 10) is formed over the waveguide. Semiconductor devices (212) are formed upon a base layer (210) over the second insulating layer and the waveguide in the second region, and an optoelectronic device (215; Fig. 10) is formed on the semiconductor layer (206; Fig. 10) in the first region.

公开(公告)号：GB2585295B

公开(公告)日：2022-06-08

申请号：GB202013202

申请日：2019-01-15

Applicant: IBM

Inventor： HARIKLIA DELIGIANNI ,  KO-TAO LEE ,  NING LI ,  DEVENDRA SADANA

IPC: A61N5/06

Abstract: Probes include a probe body configured to penetrate biological tissue. High-efficiency light sources are positioned within the probe body. Each high-efficiency light source has a sufficiently intense light output to trigger a light-sensitive reaction in neighboring tissues and has a sufficiently low power output such that a combined heat output of multiple light sources does cause a disruptive temperature increase in the neighboring tissues.

公开(公告)号：GB2599329A

公开(公告)日：2022-03-30

申请号：GB202200313

申请日：2020-06-15

Applicant: IBM

Inventor： STEVEN HOLMES ,  DEVENDRA SADANA ,  STEPHEN BEDELL

IPC: A61B5/00

Abstract: A method includes implanting an implantable biosensor within a subject where the implantable biosensor has an array of light sources and an array of light detectors, activating the array of light sources to direct light signals at a targeted tissue site in the subject, capturing, with the light detectors, the light signals reflected off the targeted site, calculating a roundtrip propagation time for each of the light signals and comparing the roundtrip propagation time for each of the light signals against previous calculated respective roundtrip propagation times to determine an occurrence of a change in the targeted tissue site.

公开(公告)号：GB2579748A

公开(公告)日：2020-07-01

申请号：GB202003124

申请日：2018-07-26

Applicant: IBM

Inventor： YUN SEOG LEE ,  DEVENDRA SADANA ,  SOUZA DE

IPC: H01M10/0525

Abstract: A solid-state lithium-based battery having fast charging and recharging speeds (above 3 C) is provided by including a nitrogen-enriched lithiated cathode material surface layer between the lithiated cathode material layer and the lithium-based solid-state electrolyte layer. The nitrogen-enriched lithiated cathode material surface layer can be formed by introducing nitrogen into a lithiated cathode material. The nitrogen can be introduced during the final stage of a deposition process or by utilizing a different process, such as, for example, thermal nitridation, than a deposition process.

公开(公告)号：GB2538348A

公开(公告)日：2016-11-16

申请号：GB201604084

申请日：2016-03-10

Applicant: IBM

Inventor： JIN CAI ,  NING LI ,  JEAN-OLIVIER PLOUCHART ,  DEVENDRA SADANA ,  TAK HUNG NING ,  EFFENDI LEOBANDUNG

IPC: H01S5/026 ,  G02B6/42 ,  G02B6/43 ,  H01L27/15

Abstract: After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate 10 of a semiconductor-on-insulator (SOI substrate 8, a dielectric waveguide material stack 22, 24, 26 including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (BJT), which can be a PNP BJT 30, an NPN BJT 40 or a pair of complementary PNP BJT 30 and NPN BJT 40, is formed in a remaining portion of the top semiconductor layer. After forming a second trench extending through the dielectric waveguide material stack to re-expose a portion of a bottom surface of the first trench, a laser diode is formed in the second trench. An optoelectronic device, for example a laser diode 60 may be formed on top of the compound semiconductor buffer layer 58 and edge coupled to the dielectric waveguide 22, 24, 26.

公开(公告)号：GB2604555A

公开(公告)日：2022-09-07

申请号：GB202208762

申请日：2020-10-22

Applicant: IBM

Inventor： YOUNG-HYE NA ,  JANGWOO KIM ,  ROBERT DAVID ALLEN ,  JOEL DE SOUZA ,  JOHN COLLINS ,  DEVENDRA SADANA

IPC: H01M10/0568 ,  H01M4/38

Abstract: A battery includes a cathode with a metal halide and an electrically conductive material, wherein the metal halide acts as an active cathode material; a porous silicon anode with a surface having pores with a depth of about 0.5 microns to about 500 microns, and a metal on the surface and in at least some of the pores thereof; and an electrolyte contacting the anode and the cathode, wherein the electrolyte includes a nitrile moiety.

公开(公告)号：GB2579748B

公开(公告)日：2022-01-19

申请号：GB202003124

申请日：2018-07-26

Applicant: IBM

Inventor： YUN SEOG LEE ,  DEVENDRA SADANA ,  SOUZA DE

IPC: H01M10/0525

Abstract: A solid-state lithium-based battery having fast charging and recharging speeds (above 3 C) is provided by including a nitrogen-enriched lithiated cathode material surface layer between the lithiated cathode material layer and the lithium-based solid-state electrolyte layer. The nitrogen-enriched lithiated cathode material surface layer can be formed by introducing nitrogen into a lithiated cathode material. The nitrogen can be introduced during the final stage of a deposition process or by utilizing a different process, such as, for example, thermal nitridation, than a deposition process.