公开(公告)号：IT7925328D0

公开(公告)日：1979-08-29

申请号：IT2532879

申请日：1979-08-29

Applicant: IBM

Inventor： CLEMEN RAINER ,  JOERG GSCHWENDTNER ,  HAUG WERNER

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

公开(公告)号：IT7927812D0

公开(公告)日：1979-12-04

申请号：IT2781279

申请日：1979-12-04

Applicant: IBM

Inventor： CLEMEN RAINER ,  JOERG GSCHWENDTNER ,  HAUG WERNER

IPC: G11C11/409 ,  G11C7/00 ,  G11C11/24 ,  G11C11/403 ,  G11C11/404 ,  G11C11/4096 ,  G11B