公开(公告)号：JP2000112753A

公开(公告)日：2000-04-21

申请号：JP11053699

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/318 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To obtain a method for operating a computer that has a milli-mode function by giving control, that enables a BHT operation to continue, to a milli-code except in the case of a specific situation where the control of an instruction fetch operation is needed. SOLUTION: A searching means 6 supplies a start address that is used when a branch history table(BHT) 5 accesses a BHT array 8 to the table (BHT) 5 which supplies information that gives an instruction to an instruction fetching means 2. Target information is latched in a register 10, and instruction address information is compared with a search address by a comparator 9. Results of the instruction address comparator 9 and a global disable latch 13 are used to decide if hit takes place and which set is desirable in hit detection logic 12. The selection of the set is used to control a multiplexer 11 and to make the instruction fetching means 2 gate correct branch target information.

公开(公告)号：JP2000099325A

公开(公告)日：2000-04-07

申请号：JP11055499

申请日：1999-04-19

Applicant: IBM

Inventor： MARK A CHECK ,  JOHN S RIPPUTAI ,  TIMOTHY J SLEEGEL ,  CHARLES F WEBB ,  MARK S FARRELL

IPC: G06F9/22 ,  G06F9/26 ,  G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a computer which has a millimode function for a system that has a central processor and also has operations of both normal mode and millimode. SOLUTION: This computer system having a millimode function gives the control to a millicode to continue a BHT(branch history table) operation excluding a case where a special situation occurs to need the control of an instruction fetch operation. A BHT 5 can be turned off to a certain section for execution of a code and cannot be disabled to all sections. A single free-running BHT functions to both normal mode and millimode used for a central processor that can be executed in a millimode by the BHT which indicates an instruction fetch containing both global BHT and millicode disabling functions.