公开(公告)号：GB2564994B

公开(公告)日：2020-12-23

申请号：GB201817748

申请日：2017-04-05

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  JONATHAN ROBERT JACKSON ,  WILLIAM STARKE ,  JEFFREY STUECHELI

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842

公开(公告)号：GB2564994A

公开(公告)日：2019-01-30

申请号：GB201817748

申请日：2017-04-05

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  JONATHAN ROBERT JACKSON ,  WILLIAM STARKE ,  JEFFREY STUECHELI

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a system wide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the system wide coherence response for the memory access request. In response to the early indication and prior to receiving the system wide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.