公开(公告)号：GB2564994B

公开(公告)日：2020-12-23

申请号：GB201817748

申请日：2017-04-05

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  JONATHAN ROBERT JACKSON ,  WILLIAM STARKE ,  JEFFREY STUECHELI

IPC: G06F12/0815 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842

公开(公告)号：GB2603447A

公开(公告)日：2022-08-03

申请号：GB202208451

申请日：2020-11-25

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  HUGH SHEN ,  LUKE MURRAY

IPC: G06F12/0806

Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush/clean memory access operation of one of a plurality of processor cores that specifies a target address, services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores such that no other coherence participant is permitted to assume coherence ownership of the memory block.

公开(公告)号：GB2546387A

公开(公告)日：2017-07-19

申请号：GB201620730

申请日：2016-12-06

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  HUGH SHEN

IPC: G06F12/1027

Abstract: This application is for a way to invalidate the entries in a translation lookaside buffer more efficiently using sidecar logic, which is a one request-buffering entry. It works by first executing a translation lookaside buffer invalidate entry instruction (TLBIE), 501, then pausing the dispatch of the TLBIE in the present thread 502. It then moves the TLBIE to the store queue of a level 2 cache 506, and once it is there moves it to the sidecar 602, 604. It then holds it there until it receives a signal that the invalidate instructions have been completed in all other processors 508, and once it has resumes the dispatch of the instructions in the thread 510. Once it is in the sidecar logic, it further broadcasts an invalidation request that is received by the plurality of processor cores, and it further ensures the completion of the processor of the translation invalidation request by broadcasting a synchronisation request.

公开(公告)号：GB2603447B

公开(公告)日：2022-11-16

申请号：GB202208451

申请日：2020-11-25

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  HUGH SHEN ,  LUKE MURRAY

IPC: G06F12/0817

Abstract: A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush/clean memory access operation of one of a plurality of processor cores that specifies a target address, services the request and thereafter enters a referee mode. While in the referee mode, the snoop logic protects a memory block identified by the target address against conflicting memory access requests by the plurality of processor cores such that no other coherence participant is permitted to assume coherence ownership of the memory block.

公开(公告)号：GB2564994A

公开(公告)日：2019-01-30

申请号：GB201817748

申请日：2017-04-05

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  JONATHAN ROBERT JACKSON ,  WILLIAM STARKE ,  JEFFREY STUECHELI

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842

Abstract: A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a system wide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the system wide coherence response for the memory access request. In response to the early indication and prior to receiving the system wide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

公开(公告)号：GB2603693A

公开(公告)日：2022-08-10

申请号：GB202205124

申请日：2020-08-20

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  HUGH SHEN

IPC: G06F3/06 ,  G06F12/08

Abstract: A data processing system includes multiple processing units coupled to a system interconnect including a broadcast address interconnect and a data interconnect. The processing unit includes a processor core that executes memory access instructions and a cache memory, coupled to the processor core, which is configured to store data for access by the processor core. The processing unit is configured to broadcast, on the address interconnect, a cache-inhibited write request and write data for a destination device coupled to the system interconnect. In various embodiments, the initial cache-inhibited request and the write data can be communicated in the same or different requests on the address interconnect.

公开(公告)号：GB2546387B

公开(公告)日：2019-08-14

申请号：GB201620730

申请日：2016-12-06

Applicant: IBM

Inventor： DEREK WILLIAMS ,  GUY GUTHRIE ,  HUGH SHEN

IPC: G06F9/30 ,  G06F12/1027

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests of a plurality of concurrently executing hardware threads are received in a shared queue. The storage-modifying requests include a translation invalidation request of an initiating hardware thread. The translation invalidation request is removed from the shared queue and buffered in sidecar logic in one of a plurality of sidecars each associated with a respective one of the plurality of hardware threads. While the translation invalidation request is buffered in the sidecar, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.