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公开(公告)号：DE69633601T2
公开(公告)日：2006-02-02
申请号：DE69633601
申请日：1996-08-09
Applicant: IBM
Inventor： ANDREWS LAWRENCE PAUL , DAVIS GORDON TAYLOR , JOHNSON WILLIE JAMES , JONES JR , LANDA ROBERT EUGENE , MANDALIA BAIJU DHIRAJLAL , SINIBALDI JOHN CLAUDE
Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.
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公开(公告)号：DE69033444T2
公开(公告)日：2000-09-07
申请号：DE69033444
申请日：1990-08-29
Applicant: IBM
Inventor： JONES JR
Abstract: The architecture of the signal processor operates the ALU (10) and MACU (11) through a register file (9) that serves as a general buffer pool for operands. All operand transfers take place between data memory through this register file (9) and ALU (10) and MACU (11) have equal access to all data in the file (9). Further the file (9) is the buffer for previous ALU results. In this manner, the bandwidths of all the individual units, data buses (19, 20), ALU (10) and MACU (11) can be fully utilized without conflicts. In general, the proposed configuration relies on the redundance or latency in many signal processing computations where data and results are used and reused in the overall computation and must remain in holding registers. The register file gives this capability providing these operands for use independently by both the ALU (10) and MACU (11). Without a common register file, operands would have to be reloaded as the computation continues. These redundant loads reduce the throughput for the computation.
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公开(公告)号：DE69633601D1
公开(公告)日：2004-11-18
申请号：DE69633601
申请日：1996-08-09
Applicant: IBM
Inventor： ANDREWS LAWRENCE PAUL , DAVIS GORDON TAYLOR , JOHNSON WILLIE JAMES , JONES JR , LANDA ROBERT EUGENE , MANDALIA BAIJU DHIRAJLAL , SINIBALDI JOHN CLAUDE
Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.
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公开(公告)号：DE69033444D1
公开(公告)日：2000-03-09
申请号：DE69033444
申请日：1990-08-29
Applicant: IBM
Inventor： JONES JR
Abstract: The architecture of the signal processor operates the ALU (10) and MACU (11) through a register file (9) that serves as a general buffer pool for operands. All operand transfers take place between data memory through this register file (9) and ALU (10) and MACU (11) have equal access to all data in the file (9). Further the file (9) is the buffer for previous ALU results. In this manner, the bandwidths of all the individual units, data buses (19, 20), ALU (10) and MACU (11) can be fully utilized without conflicts. In general, the proposed configuration relies on the redundance or latency in many signal processing computations where data and results are used and reused in the overall computation and must remain in holding registers. The register file gives this capability providing these operands for use independently by both the ALU (10) and MACU (11). Without a common register file, operands would have to be reloaded as the computation continues. These redundant loads reduce the throughput for the computation.
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Patent Agency Ranking
公开(公告)号：DE3687381D1
公开(公告)日：1993-02-11
申请号：DE3687381
申请日：1986-04-28
Applicant: IBM
Inventor： JONES JR , LEE RODNEY EDGAR , YEH TSU HSING
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公开(公告)号：DE3583256D1
公开(公告)日：1991-07-25
申请号：DE3583256
申请日：1985-02-13
Applicant: IBM
Inventor： JONES JR , LARSEN LARRY DONALD
Abstract: An improved method and apparatus for digital speech storage and retrieval systems is described which disconnects the parallel tone receiver from the reception path of the hybrid circuit during the active playback of previously recorded material. This prevents interference with incoming control signals by feedback of signals through the hybrid circuit that occurs during playback of the stored speech. A diverter switch is controlled during the playback mode to allow incoming control signals to be decoded only when gaps of sufficient length are detected in the played back program.
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公开(公告)号：DE3687381T2
公开(公告)日：1993-07-15
申请号：DE3687381
申请日：1986-04-28
Applicant: IBM
Inventor： JONES JR , LEE RODNEY EDGAR , YEH TSU HSING
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