公开(公告)号：JPH11175491A

公开(公告)日：1999-07-02

申请号：JP24160698

申请日：1998-08-27

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C JR ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F15/16 ,  G06F13/00 ,  G06F13/24 ,  G06F15/177 ,  H04L12/66 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To distribute the operation that processes transmission data of a primary speed by making a host processor read information from 2nd data memory when an interrupt is received. SOLUTION: Although 16-bits in a HBRIDGE interrupt register are usually used to represent different types of services up to sixteen, a digital signal processor(DSP) 12 sends a control block of data that represents an interrupt to be requested to a prescribed area in data memory of a controller card 4 by direct memory access process. Therefore, DSP subsystems 12 set a certain bit to send an interrupt through PCI buses 48 and 53. When the interrupt is received through an interrupt A line, a controller processor 53a decides that a DSP subsystem 12-0 requested the interrupt, and when the interrupt is received through an interrupt B line, it decides that one of DSPs 12-1 to 12-7 requested it.

公开(公告)号：DE69633601T2

公开(公告)日：2006-02-02

申请号：DE69633601

申请日：1996-08-09

Applicant: IBM

Inventor： ANDREWS LAWRENCE PAUL ,  DAVIS GORDON TAYLOR ,  JOHNSON WILLIE JAMES ,  JONES JR ,  LANDA ROBERT EUGENE ,  MANDALIA BAIJU DHIRAJLAL ,  SINIBALDI JOHN CLAUDE

IPC: G06F13/00 ,  G06F17/00 ,  H04J3/12 ,  H04J3/16 ,  H04L29/00 ,  H04L29/06

Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

公开(公告)号：DE69633601D1

公开(公告)日：2004-11-18

申请号：DE69633601

申请日：1996-08-09

Applicant: IBM

Inventor： ANDREWS LAWRENCE PAUL ,  DAVIS GORDON TAYLOR ,  JOHNSON WILLIE JAMES ,  JONES JR ,  LANDA ROBERT EUGENE ,  MANDALIA BAIJU DHIRAJLAL ,  SINIBALDI JOHN CLAUDE

IPC: G06F13/00 ,  H04J3/12 ,  H04J3/16 ,  H04L29/06 ,  H04L29/00 ,  G06F17/00

Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

公开(公告)号：DE69836307T2

公开(公告)日：2007-04-26

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

公开(公告)号：DE69836307D1

公开(公告)日：2006-12-14

申请号：DE69836307

申请日：1998-09-15

Applicant: IBM

Inventor： ANDREWS LAWRENCE P ,  BECKMAN RICHARD CLYDE ,  ENG ROBERT CHIH-TSIN ,  LINGER JUDITH MARIE ,  PETTY JOSEPH C ,  SINIBALDI JOHN CLAUDE ,  TURBEVILLE GARY L ,  WILLIAMS KEVIN BRADLEY

IPC: G06F13/24 ,  G06F15/16 ,  G06F13/00 ,  G06F15/177 ,  H04L12/66

Abstract: A pair of communications adapters each include a number of digital signal processors (12) and network interface circuits (24) for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor (2). Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.