公开(公告)号：US3610959A

公开(公告)日：1971-10-05

申请号：US3610959D

申请日：1969-06-16

Applicant: IBM

Inventor： PALMIERI JOHN A

IPC: H03K3/286 ,  H03K3/037 ,  H03K17/00 ,  H03K19/34

CPC classification number: H03K3/037

Abstract: A symmetrical direct-coupled trigger circuit comprising first and second interconnected stages, each including current switch logic means. In the first stage, a plurality of current switches have selected respective collector output lines and emitter output lines interconnected to provide logic signals at a pair of nodes; the nodes are connected to the second stage so that accompanying signal propogation is held to two stages of delay.

公开(公告)号：US3678475A

公开(公告)日：1972-07-18

申请号：US3678475D

申请日：1971-02-01

Applicant: IBM

Inventor： JORDAN PAUL V ,  PALMIERI JOHN A ,  WADE WILLIAM T

IPC: G11C17/08 ,  G11C11/40 ,  G11C17/00

CPC classification number: G11C17/08

Abstract: A method and apparatus for storing in a read only memory a matrix having one or more rows each with a majority of '''' 1'''' bits. There is formed the complement of each of those rows having a majority of '''' 1'''' bits to form a new matrix wherein no row has a majority of '''' 1'''' bits. The new matrix is stored in a read only memory. Upon reading out one or more rows of the matrix the bits of the complemented rows are reinverted.

Abstract translation: 一种用于在只读存储器中存储具有一行或多行具有多数“1”位的矩阵的方法和装置。 形成具有大多数“1”位的那些行中的每一行的互补以形成其中没有行具有多数“1”位的新矩阵。 新矩阵存储在只读存储器中。 在读取矩阵的一行或多行时，补码行的位被重新转换。

公开(公告)号：CA1133146A

公开(公告)日：1982-10-05

申请号：CA337643

申请日：1979-10-15

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H05K1/16 ,  H05K3/10

Abstract: MASTER IMAGE CHIP ORGANIZATION TECHNIQUE OR METHOD Semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of large scale integrated part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. This master image wiring structure makes it possible to personalize the power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance. FI9-78-014

公开(公告)号：CA1120606A

公开(公告)日：1982-03-23

申请号：CA326113

申请日：1979-04-23

Applicant: IBM

Inventor： BALYOZ JOHN ,  CHANG CHI S ,  FOX BARRY C ,  GHAFGHAICHI MAJID ,  JEN TEH-SEN ,  MOONEY DONALD B ,  PALMIERI JOHN A

IPC: H01L21/822 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118 ,  H01L27/10

Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices. In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.