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    Pulse width modulated voltage regulator
    1.
    发明授权
    Pulse width modulated voltage regulator 失效
    脉冲宽度调制电压调节器

    公开(公告)号：US3670234A

    公开(公告)日：1972-06-13

    申请号：US5105270

    申请日：1970-06-30

    Applicant: IBM

    Inventor： JOYCE JAMES M

    IPC: G05F1/44 ,  H02M3/337 ,  H02M3/32

    CPC classification number: H02M3/3378 ,  G05F1/44 ,  H02M1/08 ,  H02M1/32

    Abstract: A regulated power supply of the driven power inverter type. The widths of the driver pulses are controlled by a modulation waveform which varies in accordance with variations in the regulated output from the reference potential. The driver transistors are simultaneously turned on during the dwell periods of the modulation waveform to dissipate current in the windings of the interstage transformer and switch off the power transistors. The transformer is a current transformer which includes positive feedback windings on the secondary side. The turns ratio of the positive feedback winding and the secondary current winding associated with each power transistor is set equal to the inverse current gain of the transistor to ensure a fixed gain when the transistor is in saturation. A regulated low current voltage is applied to the midpoint of the primary side of the transformer to provide low power switching of the power transistors. A transistor switch connected from the regulator output to the primary side of the transformer removes the driver pulses from the inverter in the event of a component failure.

    Abstract translation: 驱动电源逆变器类型的稳压电源。 驱动脉冲的宽度由调制波形控制，该调制波形根据从参考电位的调节输出的变化而变化。 驱动晶体管在调制波形的停留期间同时导通，以耗散级间变压器的绕组中的电流并且关断功率晶体管。 变压器是一个电流互感器，它包括次级侧的正反馈绕组。 将正反馈绕组和与每个功率晶体管相关联的次级电流绕组的匝数比设置为等于晶体管的反向电流增益，以在晶体管处于饱和时确保固定增益。 调节的低电流电压被施加到变压器的初级侧的中点以提供功率晶体管的低功率开​​关。 从稳压器输出端连接到变压器初级侧的晶体管开关，在组件故障的情况下，从逆变器中消除驱动脉冲。

    2.
    发明专利
    未知

    公开(公告)号：BR9002280A

    公开(公告)日：1991-08-06

    申请号：BR9002280

    申请日：1990-05-16

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN MARIO ,  SANDERSON KENNETH R

    IPC: G06F15/16 ,  G06F9/46 ,  G06F11/00 ,  G06F11/16 ,  G06F11/20 ,  G06F12/02 ,  G06F13/368 ,  G06F15/177 ,  G06F13/00

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    4.
    发明专利
    未知

    公开(公告)号：BR9002297A

    公开(公告)日：1991-08-06

    申请号：BR9002297

    申请日：1990-05-16

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUZREZ GUSTAVO A

    IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F13/00

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    5.
    发明专利
    未知

    公开(公告)号：FR2329139A1

    公开(公告)日：1977-05-20

    申请号：FR7629486

    申请日：1976-09-22

    Applicant: IBM

    Inventor： HERKO JOSEPH M ,  JOYCE JAMES M

    IPC: H02M3/145 ,  H02M3/155 ,  H02M3/28 ,  H02M3/337 ,  H02P13/22

    Abstract: Disclosed herein is an improved pulse width modulated (PWM) voltage regulator-converter system which can function, alone, as a switched voltage regulator system or in combination with a switched power converter, synchronized therewith to form an improved voltage regulator-converter/power converter system. In the pulse width modulated voltage regulator-converter embodiment of the invention, secondary windings of a "current mode" regulator-converter interstage transformer are coupled to regulator-converter power transistors in a push-push circuit configuration. Signals generated by a system clock means and an error signal, derived from the output of an averaging filter, drive a pulse width modulated control means connected to the primary windings of the regulator-converter interstage transformer to thereby increase the maximum regulated output voltage of the voltage regulator-converter system after conditioning in the averaging filter. In the pulse width modulated voltage regulator-converter/power converter embodiment of the invention, the aforementioned output voltage of the voltage regulator-converter system is coupled directly to a switched power converter connected in a push-pull circuit configuration. In turn, additional signals generated by the system clock means switch the power converter in synchronizm with the voltage regulator-converter system.

    METHOD AND APPARATUS FOR THE DIRECT TRANSFER OF INFORMATION BETWEEN APPLICATION PROGRAMS RUNNING ON DISTINCT PROCESSORS WITHOUT UTILIZING THE SERVICES OF ONE OR BOTH OPERATING SYSTEMS
    6.
    发明专利
    METHOD AND APPARATUS FOR THE DIRECT TRANSFER OF INFORMATION BETWEEN APPLICATION PROGRAMS RUNNING ON DISTINCT PROCESSORS WITHOUT UTILIZING THE SERVICES OF ONE OR BOTH OPERATING SYSTEMS 未知

    公开(公告)号：CA2009780A1

    公开(公告)日：1990-11-17

    申请号：CA2009780

    申请日：1990-02-07

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R

    IPC: G06F15/16 ,  G06F9/46 ,  G06F15/17 ,  G06F15/173 ,  G06F15/177

    Abstract: The functions of two virtual opening systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    PROVIDING ADDITIONAL SYSTEM CHARACTERISTICS TO A DATA PROCESSING SYSTEM
    7.
    发明专利
    PROVIDING ADDITIONAL SYSTEM CHARACTERISTICS TO A DATA PROCESSING SYSTEM 未知

    公开(公告)号：CA2009549A1

    公开(公告)日：1990-11-17

    申请号：CA2009549

    申请日：1990-02-07

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R

    IPC: G06F15/16 ,  G06F12/02 ,  G06F13/38

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    8.
    发明专利
    未知

    公开(公告)号：FR2329100A1

    公开(公告)日：1977-05-20

    申请号：FR7627613

    申请日：1976-09-06

    Applicant: IBM

    Inventor： JOYCE JAMES M

    IPC: G05F1/56 ,  H02M3/156 ,  H02M3/28 ,  H02M3/338 ,  H02P13/24 ,  H02M3/335

    Abstract: Instability effects over a wide range of static load current conditions in a conventional pulse width modulated (PWM) voltage regulator-converter/power converter circuit configuration having cascaded LC-LC filter networks are eliminated by replacing an inductor, in the averaging filter section of the voltage regulator-converter with the primary winding of a transinductor and by placing the secondary winding thereof in series with an inductor in the output filter section of the power converter. The aforementioned transinductor, in combination with other elements of the system, is designed and configurated such that the closed-loop stability characteristics approach that of a two pole system while maintaining the superior filtering characteristics of a four pole system.

    9.
    发明专利
    未知

    公开(公告)号：BR9002305A

    公开(公告)日：2005-02-01

    申请号：BR9002305

    申请日：1990-05-17

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  JOYCE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  BAKER ERNEST D

    IPC: G06F15/16 ,  G06F9/46 ,  G06F15/17 ,  G06F15/173 ,  G06F15/177 ,  G06F13/14

    Abstract: The functions of two virtual opening systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

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