公开(公告)号：JP2001267421A

公开(公告)日：2001-09-28

申请号：JP2001032183

申请日：2001-02-08

Applicant: IBM

Inventor： JUAN A CHEDEIAKKU ,  RANDY W MANN ,  SLINKMAN JAMES A

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To self-align to the gate structure of a field effect transistor, and prevent the occurrence of electric short-circuiting when a conductive stud is formed in a drain or source region. SOLUTION: On the surface of a semiconductor substrate 20, a gate dielectric 32, gate structure 30 consisting of a conductive gate 34 that is matched to the gate dielectric and an insulation cap 38 are formed, and drain and source regions 42 and 44 are formed. After insulation spacers 52 and 54 are formed on the side wall of the gate structure 30, an insulation region that is made of a nitride blanket 60, and bonate-prosphste-silicate glass is formed, and the insulation region is polished and flattened by the CMP method up to the nitride blanket 60. Then, with a resist pattern as a mask, the insulation region and the nitride blanket 60 are etched to form a cavity above the drain and source regions, and the cavity is filled with a conductive material to form conductive studs 92 and 94. The surface of the conductive studs 92 and 94 is coplanar with that of the gate structure 30.