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    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    3.
    发明专利
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001267421A

    公开(公告)日：2001-09-28

    申请号：JP2001032183

    申请日：2001-02-08

    Applicant: IBM

    Inventor： JUAN A CHEDEIAKKU ,  RANDY W MANN ,  SLINKMAN JAMES A

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To self-align to the gate structure of a field effect transistor, and prevent the occurrence of electric short-circuiting when a conductive stud is formed in a drain or source region. SOLUTION: On the surface of a semiconductor substrate 20, a gate dielectric 32, gate structure 30 consisting of a conductive gate 34 that is matched to the gate dielectric and an insulation cap 38 are formed, and drain and source regions 42 and 44 are formed. After insulation spacers 52 and 54 are formed on the side wall of the gate structure 30, an insulation region that is made of a nitride blanket 60, and bonate-prosphste-silicate glass is formed, and the insulation region is polished and flattened by the CMP method up to the nitride blanket 60. Then, with a resist pattern as a mask, the insulation region and the nitride blanket 60 are etched to form a cavity above the drain and source regions, and the cavity is filled with a conductive material to form conductive studs 92 and 94. The surface of the conductive studs 92 and 94 is coplanar with that of the gate structure 30.

    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGRATED DEVICES
    4.
    发明申请
    SYSTEM AND METHOD FOR DETECTING LOCAL MECHANICAL STRESS IN INTEGRATED DEVICES 审中-公开
    用于检测集成设备中的局部机械应力的系统和方法

    公开(公告)号：WO2009111163A3

    公开(公告)日：2010-01-21

    申请号：PCT/US2009034350

    申请日：2009-02-18

    Applicant: IBM ,  BUMM LLOYD ,  DAHAYANAKA DAMINDA ,  KASZUBA PHILIP V ,  MOSZKOWICZ LEON ,  SLINKMAN JAMES A

    Inventor： BUMM LLOYD ,  DAHAYANAKA DAMINDA ,  KASZUBA PHILIP V ,  MOSZKOWICZ LEON ,  SLINKMAN JAMES A

    IPC: G01N21/86

    CPC classification number: G01B21/32 ,  G01Q60/30

    Abstract: A method of detecting local mechanical stress in integrated devices is provided, the method comprising: enabling the detection of a photo voltage difference between a scan probe device (14) and a surface portion (30) of an integrated device (18), the scan probe device (14) being configured to deflect in response to the photo voltage difference; measuring the deflection of the scan probe device (14) in response to the photo voltage difference between the scan probe device (14) and the surface portion (30) of the integrated device (18); and calculating a local stress level within the integrated device by determining a local work function of the surface portion (30) of the integrated device (18) based upon the deflection of the scan probe device (14).

    Abstract translation: 提供了一种在集成器件中检测局部机械应力的方法，所述方法包括：能够检测扫描探针器件（14）与集成器件（18）的表面部分（30）之间的光电压差，扫描 探针装置（14）被配置为响应于光电压差而偏转; 响应于扫描探针装置（14）和集成装置（18）的表面部分（30）之间的光电压差，测量扫描探针装置（14）的偏转; 以及基于所述扫描探针装置（14）的偏转来确定所述集成装置（18）的所述表面部分（30）的局部功函数来计算所述集成装置内的局部应力水平。

    SEMICONDUCTOR DEVICE STRUCTURE HAVING REDUCED INTER- WELL LEAK, AND METHOD OF FORMING THE SAME
    6.
    发明专利
    SEMICONDUCTOR DEVICE STRUCTURE HAVING REDUCED INTER- WELL LEAK, AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：JP2002313907A

    公开(公告)日：2002-10-25

    申请号：JP2002040159

    申请日：2002-02-18

    Applicant: IBM

    Inventor： LOGAN LYNDON R ,  SLINKMAN JAMES A

    IPC: H01L21/76 ,  H01L21/761 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which is reduced in inter-well leak. SOLUTION: The method for forming a semiconductor device having improved leak controllability includes steps of preparing a semiconductor substrate, forming a trench in the substrate, forming a leakage/stop/implant positioned under one sidewall of the trench in the substrate under the bottom surface of the trench, filling an insulator into the trench, and forming an N well (or P well) contacted with the other sidewall of the trench opposed to the above sidewall. The N well (or P well) is extended below the trench to form an upper part of a separate junction from the leakage/stop/implant, and the upper part of the separate junction is positioned completely under the trench. The leak control implant is self-aligned with the sidewall of the trench.

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
    8.
    发明申请
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 审中-公开
    用于降低谐波的硅绝缘体（SOI）结构，设计结构和方法

    公开(公告)号：WO2011066035A3

    公开(公告)日：2011-07-28

    申请号：PCT/US2010050805

    申请日：2010-09-30

    Applicant: IBM ,  BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

    Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

    IPC: H01L27/12

    CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203

    Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

    Abstract translation: 公开了在半导体衬底（110）上具有绝缘体层（120）并且器件层（130）位于绝缘体层上的半导体结构（100）。 衬底（110）掺杂有相对低剂量的具有给定导电类型的掺杂剂（111），使得其具有相对高的电阻率。 此外，紧邻绝缘体层的半导体衬底的一部分（102）可以用稍高剂量的相同掺杂剂（111），具有相同导电类型的不同掺杂剂（112）或其组合（111 和112）。 可选地，在该相同部分（102）内形成微腔（122,123），以平衡电导率的任何增加以及电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度提高了任何得到的寄生电容器的阈值电压（Vt），从而降低了谐波行为。 在此还公开了用于这种半导体结构的方法和设计结构的实施例。

    SCALING OF BIPOLAR TRANSISTORS
    9.
    发明申请
    SCALING OF BIPOLAR TRANSISTORS 审中-公开
    双极晶体管的放大

    公开(公告)号：WO2011008359A3

    公开(公告)日：2011-03-10

    申请号：PCT/US2010037149

    申请日：2010-06-03

    Applicant: IBM ,  JOSEPH ALVIN J ,  MALLADI RAMANA M ,  SLINKMAN JAMES A

    Inventor： JOSEPH ALVIN J ,  MALLADI RAMANA M ,  SLINKMAN JAMES A

    IPC: H01L21/331 ,  H01L29/73

    CPC classification number: H01L29/66272 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8249 ,  H01L27/0207 ,  H01L29/7322 ,  Y02P90/265

    Abstract: Bipolar transistor structures, methods of designing and fabricating bipolar transistors, methods of designing circuits having bipolar transistors. The method of designing the bipolar transistor includes: selecting an initial design of a bipolar transistor (240 of FIG. 18); scaling the initial design of the bipolar transistor to generate a scaled design of the bipolar transistor (245); determining if stress compensation of the scaled design of the bipolar transistor is required based on dimensions of an emitter of the bipolar transistor after the scaling (250); and if stress compensation of the scaled design of the bipolar transistor is required then adjusting a layout of a trench isolation layout level of the scaled design relative to a layout of an emitter layout level of the scaled design (255) to generate a stress compensated scaled design of the bipolar transistor (260).

    Abstract translation: 双极晶体管结构，双极晶体管的设计和制造方法，设计具有双极晶体管的电路的方法。 设计双极晶体管的方法包括：选择双极晶体管（图18的240）的初始设计; 缩放双极晶体管的初始设计以产生双极晶体管（245）的缩放设计; 确定在缩放之后双极晶体管的发射极的尺寸（250）是否需要双极晶体管的缩放设计的应力补偿; 并且如果需要对双极晶体管的缩放设计的应力补偿，则调整缩放设计的沟槽隔离布局级别相对于缩放设计（255）的发射器布局级别的布局的布局，以产生应力补偿缩放 双极晶体管（260）的设计。

    Verfahren, Vorrichtung und Entwurfsstruktur für eine Silicium-auf-Isolator-Schaltung mit hoher Bandbreite und verringerter Ladungsschicht
    10.
    发明专利
    Verfahren, Vorrichtung und Entwurfsstruktur für eine Silicium-auf-Isolator-Schaltung mit hoher Bandbreite und verringerter Ladungsschicht 未知

    公开(公告)号：DE112011102071T5

    公开(公告)日：2013-03-21

    申请号：DE112011102071

    申请日：2011-07-28

    Applicant: IBM

    Inventor： JOSEPH ALVIN J ,  BOTULA ALAN B ,  SLINKMAN JAMES A ,  WOLF RANDY L

    IPC: H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12

    Abstract: Ein Verfahren, ein integrierter Schaltkreis und eine Entwurfsstruktur umfassen eine Siliciumsubstratschicht (102), welche Grabenstrukturen (106) und eine Implantation ionischer Verunreinigungen (108) aufweist. Auf der Siliciumsubstratschicht wird eine Isolatorschicht (110) angebracht und mit ihr verbunden. Die Isolatorschicht (110) füllt die Grabenstrukturen (106). Auf der vergrabenen Isolatorschicht (110) wird eine Schaltungsschicht angebracht und mit ihr verbunden. Die Schaltungsschicht weist Gruppen aktiver Schaltkreise (112) auf, die durch passive Strukturen (114) voneinander getrennt sind. Die Grabenstrukturen (106) werden zwischen den Gruppen aktiver Schaltkreise (112) platziert, wenn die Struktur integrierter Schaltkreise in der Ansicht von oben betrachtet wird. Folglich sind die Grabenstrukturen (106) unter den passiven Strukturen (114) und sie sind nicht unter den Gruppen der Schaltkreise, wenn die Struktur integrierter Schaltkreis in der Ansicht von oben betrachtet wird.

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