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    Detection device for alpha particle or cosmic ray
    1.
    发明专利
    Detection device for alpha particle or cosmic ray 有权
    ALPHA颗粒或COSMIC RAY的检测装置

    公开(公告)号：JP2006024330A

    公开(公告)日：2006-01-26

    申请号：JP2004203670

    申请日：2004-07-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FIFIELD JOHN A ,  KARTSCHOKE PAUL D ,  KLAASEN WILLIAM A ,  KOSONOCKY STEPHEN V ,  RANDY W MANN ,  OPPOLD JEFFERY H ,  ROHRER NORMAN J

    IPC: G11C11/41 ,  G01T1/17 ,  G11C29/04 ,  H01L21/8238 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To provide a detection circuit and a method for detecting silicon well voltage or current indicating collision of an alpha particle or a cosmic ray to the silicon well in silicon substrate.
    SOLUTION: An effective application of the detection circuit is use in redundancy repair latches used for an SRAM. In the redundancy repair latches, normally writing is once performed when power is on in order to register wrong latch data, though writing is not performed again usually. When either state of these latches is altered by SER phenomena (soft error rate: collision of the alpha particle or the cosmic ray, and the like), the recovery data for the redundant latch of the SRAM is mapped incorrectly. In this detection circuit and the method, whether the SER phenomenon occurs in these latches is monitored, when occurring, reloading the recovery data is performed to the redundancy repair latches.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供检测电路和检测硅阱电压或电流的方法，所述硅阱电压或电流指示α粒子或宇宙射线与硅衬底中的硅阱的碰撞。

    解决方案：检测电路的有效应用是用于SRAM的冗余修复锁存器中。 在冗余修复锁存器中，通常只有在通电时才进行写入操作，才能注册错误的锁存器数据，但通常不会再写入。 当这些锁存器的任一状态被SER现象（软错误率：α粒子或宇宙射线的碰撞等）改变时，SRAM的冗余锁存器的恢复数据被映射不正确。 在该检测电路和方法中，监视这些锁存器中是否发生SER现象，发生时，对冗余修复锁存器进行恢复数据的重新加载。 版权所有（C）2006，JPO＆NCIPI

    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    2.
    发明专利
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效

    公开(公告)号：JP2001267421A

    公开(公告)日：2001-09-28

    申请号：JP2001032183

    申请日：2001-02-08

    Applicant: IBM

    Inventor： JUAN A CHEDEIAKKU ,  RANDY W MANN ,  SLINKMAN JAMES A

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To self-align to the gate structure of a field effect transistor, and prevent the occurrence of electric short-circuiting when a conductive stud is formed in a drain or source region. SOLUTION: On the surface of a semiconductor substrate 20, a gate dielectric 32, gate structure 30 consisting of a conductive gate 34 that is matched to the gate dielectric and an insulation cap 38 are formed, and drain and source regions 42 and 44 are formed. After insulation spacers 52 and 54 are formed on the side wall of the gate structure 30, an insulation region that is made of a nitride blanket 60, and bonate-prosphste-silicate glass is formed, and the insulation region is polished and flattened by the CMP method up to the nitride blanket 60. Then, with a resist pattern as a mask, the insulation region and the nitride blanket 60 are etched to form a cavity above the drain and source regions, and the cavity is filled with a conductive material to form conductive studs 92 and 94. The surface of the conductive studs 92 and 94 is coplanar with that of the gate structure 30.

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