公开(公告)号：JP2000133788A

公开(公告)日：2000-05-12

申请号：JP21479399

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： ALSMEIER JOHANN ,  BRONNER GARY ,  KAPLITA GEORGE A ,  KLEINHENZ RICHARD ,  MULLER PAUL K ,  RANADE RAJIV M ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obviate the need for etching redesigning by laying out a deep trench pattern by using a dummy semiconductor material loading rate, that is obtained by subtracting a device trench level semiconductor material loading rate from an estimated final trench level semiconductor material loading rate. SOLUTION: First, a final chip design silicon loading rate is estimated, and a plurality of device deep trenche patterns are laid out, that constitute an integrated circuit chip 14 to be developed. These trenches cumulatively have device silicon loading rates. Next, the device silicon loading rate is subtracted from the the estimated final chip design loading rate so as to compute a dummy silicon loading rate, and cumulative silicon loading rates are used to lay out a plurality of dummy deep trenches 22. It is preferable have the device trenches disperse uniformly and the dummy trenches over a chip.

公开(公告)号：CA1250669A1

公开(公告)日：1989-02-28

申请号：CA549183

申请日：1987-10-13

Applicant: IBM

Inventor： GIAMMARCO NICHOLAS J ,  GIMPELSON ALEXANDER ,  KAPLITA GEORGE A ,  LOPATA ALEXANDER D ,  SCADUTO ANTHONY F ,  SHEPARD JOSEPH F

IPC: H01L21/302 ,  G03F7/40 ,  H01L21/027 ,  H01L21/033 ,  H01L21/266 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/70

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls. In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.