公开(公告)号：JP2001358224A

公开(公告)日：2001-12-26

申请号：JP2001133328

申请日：2001-04-27

Applicant: IBM

Inventor： KARL J REEDENSU ,  BRINTZINGER AXEL C

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an interconnect structure with which an anti-fuse material layer is formed in the structure without using any precise lithography masking level. SOLUTION: This interconnect structure, in its inside of which an anti-fuse dielectric layer is formed, comprises a substrate 50 containing electrically conductive structures of a first level, a patterned anti-fuse dielectric layer 54 which is formed on the substrate 50 and which contains an opening to at least one of the electrically conductive structures 52 of a first level, a patterned interlevel dielectric layer 56 which is formed on the patterned anti-fuse dielectric layer 54 and which contains a plurality of vias, at least one of which is formed in the upper side of the opening with a via space, and electrically conductive structures 52 of a second level formed in the vias and the via space.

公开(公告)号：JP2001035860A

公开(公告)日：2001-02-09

申请号：JP2000179287

申请日：2000-06-15

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  KARL J REEDENSU

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To solve the problems associated with strap formation (e.g. conductive connection between a storage device and the gate-drain of a transistor) by connecting a transistor electrically with a storage capacitor through the outward diffusion region of a conductive strap. SOLUTION: A conductive strap 800 extends laterally from a vertical storage capacitor 103. A channel region 1300 is located on the outside of the vertical storage capacitor 103 and extending along a vertical surface shifted laterally therefrom. In the operation, the voltage on one gate conductor of a gate conductor stack causes to conduct a P well adjacent to a step part 1300 in a substrate to form a connection between two diffusion regions (e.g. source and drain). In the process, electrical connection is made between the contact bit line and the storage device 103 through a vertical transistor formed along the strap 1300 through the strap 800.

公开(公告)号：JP2006253684A

公开(公告)日：2006-09-21

申请号：JP2006061418

申请日：2006-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDRA DEIBAKARUNI ,  HO HERBERT L ,  KARL J REEDENSU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provides a structure including a trench capacitor array at least part of which is arranged under an embedded oxide layer of an SOI substrate.
SOLUTION: Each trench capacitor shares a common unitary embedded capacitor plate including at least part of a first unitary semiconductor region arranged under an embedded oxide layer. An upper boundary of the embedded capacitor plate defines a plane extending laterally over the whole trench capacitor array parallel to the major surface of a substrate. In a particular embodiment starting at an SOI substrate or a bulk substrate, the trench array and contact holes are formed at the same time such that the contact holes extend in the same depth as that of the trenches. Preferably, the width of the contact hole is substantially large compared with that of the trench, thereby forming conductive contact vias at the same time by processing used for forming a trench capacitor extending along the wall of the trench.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括沟槽电容器阵列的结构，其至少一部分布置在SOI衬底的嵌入式氧化物层的下方。 解决方案：每个沟槽电容器共享共同的单一嵌入式电容器板，其包括布置在嵌入式氧化物层下方的第一单元半导体区域的至少一部分。 嵌入式电容器板的上边界限定了平行于衬底的主表面的整个沟槽电容器阵列上横向延伸的平面。 在从SOI衬底或体衬底开始的特定实施例中，沟槽阵列和接触孔同时形成，使得接触孔在与沟槽的深度相同的深度上延伸。 优选地，接触孔的宽度与沟槽的宽度相比基本上大，由此通过用于形成沿沟槽壁延伸的沟槽电容器的处理同时形成导电接触孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2002050701A

公开(公告)日：2002-02-15

申请号：JP2001197112

申请日：2001-06-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： THOMAS W DAYER ,  LOUIS L SHEW ,  DAVID L KOTEKI ,  KARL J REEDENSU ,  GERHARD KUNKEL ,  LI HONG ,  YOUNG LIM ,  YON JIN PAKU

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM cell which eliminates critical photolithorgraphic fabrication steps by merging stacked capacitor construction with electrical contacts, and to provide a method of fabrication thereof. SOLUTION: It is sufficient to conduct in one lithography step to form electrical contacts, because the stacked capacitors are on the same plane as bit lines and the stacked capacitors are located in a insulating material provided between the bit lines. Unlike the conventional capacitor-over-bit line(COB) DRAM cells having the capacitors on the bit lines, this DRAM cell having capacitors adjacent to the bit lines eliminates the need to have dedicated contacts in the capacitor, making it possible to realize higher capacitance with lower global topography.