公开(公告)号：EP0656655A3

公开(公告)日：1998-07-29

申请号：EP94480094

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10829

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

Abstract translation: 具有浅沟槽隔离的深沟槽型DRAM单元具有掩埋多晶硅带，其被限定为不使用单独的掩模，通过在浅沟槽清晰度之前在至少深沟槽上沉积带材料并且使用浅沟槽隔离掩模部分地重叠 深沟槽，从而在切割浅沟槽的过程中限定带。

公开(公告)号：DE69431867D1

公开(公告)日：2003-01-23

申请号：DE69431867

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：SG44361A1

公开(公告)日：1997-12-19

申请号：SG1995002309

申请日：1992-12-21

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A high density substrate plate DRAM cell memory device and process are described in which a buried plate region (32) is formed adjacent to deep trench (22) capacitors such that the substrate region of DRAM transfer FETs (12) can be electrically isolated from other FETs on a semiconductor substrate (10). The buried region (32) is partially formed by lateral outdiffusion from the sidewalls of the deep trenches (22) and partially formed by an N-well surface diffusion (34) which entirely surrounds the DRAM array region.

公开(公告)号：DE68922424T2

公开(公告)日：1996-02-01

申请号：DE68922424

申请日：1989-02-06

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

Abstract: A charge amplifying memory cell and its method of making based on trench technology. A trench is formed which reaches through an n-type well region (32) to a p -type substrate (30). A triple layer (36, 38, 40) is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon (42), facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p transistor drain (44) is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p transistor source (50) is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region (46) is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.

公开(公告)号：DE3789416D1

公开(公告)日：1994-04-28

申请号：DE3789416

申请日：1987-10-16

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

Abstract: A one-device shared trench memory cell, in which the polysilicon (22,24) and dielectric layers (26,26A) within the trench (20) extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder (36). The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide a bridge contact (30) that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode (34) to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

公开(公告)号：BR8705231A

公开(公告)日：1988-05-24

申请号：BR8705231

申请日：1987-10-02

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/04 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/94

Abstract: A semiconductor trench capacitor structure (240) having a self-aligned isolation structure formed within the trench. The trench isolation structure consists of a thick isolating layer (340, 360) formed along the upper portion of the trench side walls. The trench isolation structure facilitates the construction of trench capacitors of greater storage capacity in a given space and allows the capacitors to abut adjacent capacitors and other devices.

公开(公告)号：BR8604548A

公开(公告)日：1987-05-26

申请号：BR8604548

申请日：1986-09-23

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L23/04 ,  H01L23/08

Abstract: A memory cell (10) formed in a groove or trench (18) in a semiconductor substrate (26) is provided which includes a storage capacitor (30) located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line (32) disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device (34) or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field (36) for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.

公开(公告)号：DE3268109D1

公开(公告)日：1986-02-06

申请号：DE3268109

申请日：1982-06-29

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/535 ,  H01L27/108 ,  H01L29/78 ,  H01L21/82

Abstract: A dynamic memory is provided having a cell with an improved structure and made by an improved process which substantially reduces the capacitance of the bit/sense fine connected to the cell. The cell has one field effect transistor and a storage node, and the cell structure includes a thick insulating segment located under a portion of a conductive layer or field shield and under a portion of the gate electrode of the transistor, while extending over the entire diffusion region of the bit/sense line and over substantially the entire depletion region surrounding the bit/ sense line diffusion region.

公开(公告)号：DE3172663D1

公开(公告)日：1985-11-21

申请号：DE3172663

申请日：1981-06-25

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/74 ,  H01L29/749 ,  H01L29/78 ,  H01L21/82 ,  H01L21/90 ,  H01L21/28 ,  H01L21/60

Abstract: 0 A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer (16) having a plurality of parallel thick (16a) and thin regions (16b). Perpendicular strip-like regions (16c) of masking layer (16) are removed to expose square apertures on the surface of substrate (10, 14) in which recesses (18) are formed by an anisotropic etchant. V-MOSFET devices having self- aligned gate electrodes are formed in the recesses (18) and device interconnecting lines are formed under the remaining portions of the thin regions (16b). A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of the recesses.

公开(公告)号：DE68922424D1

公开(公告)日：1995-06-08

申请号：DE68922424

申请日：1989-02-06

Applicant: IBM

Inventor： KENNEY DONALD MCALPINE

IPC: G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24

Abstract: A charge amplifying memory cell and its method of making based on trench technology. A trench is formed which reaches through an n-type well region (32) to a p -type substrate (30). A triple layer (36, 38, 40) is formed on two sidewalls of the trench consisting of two capacitive insulating layers and a intermediate p polysilicon layer. The trench is then at least partially filled with a conductor, such as polysilicon (42), facing the triple layer. Thereby, the intermediate polysilicon layer acts as a charge storage node with capacitance to both the substrate and the polysilicon filling the trench. The insulating layer facing the well is opened with a contact hole near its top so that a p transistor drain (44) is formed in the adjacent well by diffusion from the polysilicon through the contact hole. A p transistor source (50) is doped into the well with a gate region between it and the drain to provide a write transistor. A p+ region (46) is also formed adjacent a sidewall of the trench other than the one containing the contact hole so that a read transistor is vertically formed in the n-type well between it and the substrate. The intermediate p polysilicon layer acts as the electrode of this read transistor, whereby stored charge is amplified by the read transistor.