公开(公告)号：EP0656655A3

公开(公告)日：1998-07-29

申请号：EP94480094

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC classification number: H01L27/10829

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

Abstract translation: 具有浅沟槽隔离的深沟槽型DRAM单元具有掩埋多晶硅带，其被限定为不使用单独的掩模，通过在浅沟槽清晰度之前在至少深沟槽上沉积带材料并且使用浅沟槽隔离掩模部分地重叠 深沟槽，从而在切割浅沟槽的过程中限定带。

公开(公告)号：JPH11317459A

公开(公告)日：1999-11-16

申请号：JP2115999

申请日：1999-01-29

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a dual-gate oxide which is capable of manufacturing a single integrated circuit chip, wherein a logic circuit and a DRAM are combined and manufacturing a field effect transistor(FET) having a dual work function. SOLUTION: First, a thick gate oxide layer 104 is formed on a wafer, than a doped polysilicon layer 106, a silicide tungsten layer 108 and a nitride layer 110 are successively laminated on the oxide layer in order to form a gate stack. A part of the stack is selectively removed, and the wafer on which the logic circuits are formed in re-exposed. A thin gate oxide layer 116 is formed on the re-exposed region of the wafer, a polysilicon gate 120 is formed thereon, and a thick oxide NFET and PFET are formed on the gate. A thick oxide device region is selectively changed into a silicide 146, then the gate is etched from the stack in the thick oxide device region. Finally, dopant ions are implanted into source/drain regions 140 and 142 of the thick gate oxide device and are made to diffuse, and a deep junction and a dual work function gate are formed.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.

公开(公告)号：DE69431867T2

公开(公告)日：2003-10-02

申请号：DE69431867

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：DE69431867D1

公开(公告)日：2003-01-23

申请号：DE69431867

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：DE69229717T2

公开(公告)日：2000-03-02

申请号：DE69229717

申请日：1992-12-24

Applicant: IBM

Inventor： BRONNER GARY BELA ,  DHONG SANG HOO ,  HWANG WEI ,  PARK JONG WOO ,  VOLDMAN STEVEN HOWARD

IPC: H01L27/108

公开(公告)号：SG70142A1

公开(公告)日：2000-01-25

申请号：SG1998005847

申请日：1998-12-16

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY PETER ,  MANDELMAN JACK ALLAN ,  RADENS CARL J ,  TONTI WILLIAM ROBERT PATRICK

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/8238

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

公开(公告)号：MY118598A

公开(公告)日：2004-12-31

申请号：MYPI9804916

申请日：1998-10-28

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: A METHOD OF FORMING INTEGRATED CIRCUIT CHIPS INCLUDING TWO DISSIMILAR TYPE NFETS AND/OR TWO DISSIMILAR TYPE PFETS ON THE SAME CHIP, SUCH AS BOTH THICK AND THIN GATE OXIDE FETS. A DRAM ARRAY MAY BE CONSTRUCTED OF THE THICK OXIDE FETS AND LOGIC CIRCUITS MAY BE CONSTRUCTED OF THE THIN OXIDE FETS ON THE SAME CHIP. FIRST, A GATE STACK (100) INCLUDING A FIRST, THICK GATE SIO21AYER (104) IS FORMED ON A WAFER. THE STACK INCLUDES A DOPED POLYSILICON LAYER (106) ON THE GATE OXIDE LAYER, A SILICIDE LAYER (108) ON THE POLYSILICON LAYER AND A NITRIDE LAYER (110) ON THE SILICIDE LAYER. PART OF THE STACK IS SELECTIVELY REMOVED TO RE-EXPOSE THE WAFER WHERE LOGIC CIRCUITS ARE TO BE FORMED. A THINNER GATE OXIDE LAYER (116) IS FORMED ON THE RE-EXPOSED WAFER. NEXT, GATES ARE FORMED ON THE THINNER GATE OXIDE LAYER AND THIN OXIDE NFETS AND PFETS ARE FORMED AT THE GATES. AFTER SELECTIVELY SILICIDING THIN OXIDE DEVICE REGIONS, GATES ARE ETCHED FROM THE STACK IN THE THICK OXIDE DEVICE REGIONS. FINALLY, SOURCE AND DRAIN REGIONS (140, 142) ARE IMPLANTED AND DIFFUSED FOR THE THICK GATE OXIDE DEVICES.(FIG. 7)

公开(公告)号：SG70150A1

公开(公告)日：2000-01-25

申请号：SG1999000336

申请日：1999-02-03

Applicant: IBM

Inventor： BRONNER GARY BELA ,  EL-KAREH BADIH ,  SCHUSTER STANLEY EVERETT

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108

Abstract: A method of forming integrated circuit chips including two dissimilar type NFETs and/or two dissimilar type PFETs on the same chip, such as both thick and thin gate oxide FETs. A DRAM array may be constructed of the thick oxide FETs and logic circuits may be constructed of the thin oxide FETs on the same chip. First, a gate stack including a first, thick gate SiO2 layer is formed on a wafer. The stack includes a doped polysilicon layer on the gate oxide layer, a silicide layer on the polysilicon layer and a nitride layer on the silicide layer. Part of the stack is selectively removed to re-expose the wafer where logic circuits are to be formed. A thinner gate oxide layer is formed on the re-exposed wafer. Next, gates are formed on the thinner gate oxide layer and thin oxide NFETs and PFETs are formed at the gates. After selectively siliciding thin oxide device regions, gates are etched from the stack in the thick oxide device regions. Finally, source and drain regions are implanted and diffused for the thick gate oxide devices.

公开(公告)号：SG68008A1

公开(公告)日：1999-10-19

申请号：SG1997004577

申请日：1997-12-19

Applicant: IBM

Inventor： GAMBINO JEFFERY PETER ,  BRONNER GARY BELA ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY ALAN

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8232 ,  H01L27/085

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.