公开(公告)号：WO2004112041A3

公开(公告)日：2005-05-12

申请号：PCT/EP2004050867

申请日：2004-05-19

Applicant: IBM ,  IBM FRANCE ,  HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C5/14 ,  G11C8/08

CPC classification number: G11C5/143 ,  G11C8/08

Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Abstract translation: 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线中的各个字线的选择器线 驱动程序。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的电源管理电路连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：AT420439T

公开(公告)日：2009-01-15

申请号：AT04741612

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14

公开(公告)号：DE602004018924D1

公开(公告)日：2009-02-26

申请号：DE602004018924

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14