公开(公告)号：WO2004112041A3

公开(公告)日：2005-05-12

申请号：PCT/EP2004050867

申请日：2004-05-19

Applicant: IBM ,  IBM FRANCE ,  HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C5/14 ,  G11C8/08

CPC classification number: G11C5/143 ,  G11C8/08

Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Abstract translation: 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线中的各个字线的选择器线 驱动程序。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的电源管理电路连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：DE602004018924D1

公开(公告)日：2009-02-26

申请号：DE602004018924

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14

公开(公告)号：DE60035630D1

公开(公告)日：2007-09-06

申请号：DE60035630

申请日：2000-01-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

公开(公告)号：AT420439T

公开(公告)日：2009-01-15

申请号：AT04741612

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14

公开(公告)号：DE10315050A1

公开(公告)日：2003-11-27

申请号：DE10315050

申请日：2003-04-02

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE10315050B4

公开(公告)日：2009-04-23

申请号：DE10315050

申请日：2003-04-02

Applicant: IBM ,  QIMONDA AG

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD ,  HANSON DAVID

IPC: H03K19/0185 ,  H03L5/00

Abstract: A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

公开(公告)号：DE60035630T2

公开(公告)日：2008-02-07

申请号：DE60035630

申请日：2000-01-22

Applicant: IBM ,  QIMONDA NORTH AMERICA CORP

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C7/00 ,  G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.