公开(公告)号：WO2004112041A3

公开(公告)日：2005-05-12

申请号：PCT/EP2004050867

申请日：2004-05-19

Applicant: IBM ,  IBM FRANCE ,  HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C5/14 ,  G11C8/08

CPC classification number: G11C5/143 ,  G11C8/08

Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.

Abstract translation: 存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线中的各个字线的选择器线 驱动程序。 具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的电源管理电路连接到字线驱动器，以根据掉电输入信号降低其功耗。

公开(公告)号：JPH1174241A

公开(公告)日：1999-03-16

申请号：JP18232498

申请日：1998-06-29

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  WOLFGANG BERGNER ,  FIEGL BERNHARD ,  GEORGE R GOSSE ,  PARRIES PAUL ,  MATTHEW J SENDERBACH ,  TEIN-HAO WAN ,  WILLIAM C WILL ,  JUERGEN WITTMANN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To prevent damages to a substrate under a pad nitride layer, induced by CMP, by disposing the pad nitride layer under a conformally vapor-deposited dielectric layer and partly etching a first region on the dielectric layer disposed under a conformally vapor-deposited polysilicon layer, for removing the polysilicon layer. SOLUTION: A pad nitride layer 118 is evaporated onto a silicon mesa 114, and a TEOS layer (dielectric layer) 126 is evaporated conformally onto the pad nitride layer 118 and a silicon substrate 112. In addition, a polysilicon layer 130 is conformally evaporated onto the TEOS 126. Then, chemical and mechanical polishing(CMP) is used to planarize the polysilicon layer 130 downward to the surface of the TEOS layer 126, and a first region on the TEOS layer 126 disposed on the pad nitride 118 is thereby exposed. Further, the first region on the TEOS layer 126 is partly etched, using a first etching parameter, and thereafter the polysilicon layer 130 is removed.

公开(公告)号：JP2000031486A

公开(公告)日：2000-01-28

申请号：JP17744799

申请日：1999-06-23

Applicant: SIEMENS AG ,  IBM

Inventor： PARRIES PAUL ,  LIEBMAN LARS ,  THANH LIEM DO

IPC: H01L21/28 ,  H01L21/76 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce an operation of several electrons entrapped at a barrier liner by setting a gate electrode arranged on a gate channel region to a longer length on an opposed sidewall than a width of a trench on an opposed sidewall and a length on a region between opposed sidewalls. SOLUTION: Gate electrodes 50 are arranged on a gate channel region 36. The electrodes 50 have width W extended on opposed sidewalls 51 of a trench and different lengths L1, L2 on opposed sidewalls 51. The length L1 on the sidewall of the trench is larger than that L2 on a region between the opposed sidewalls 51. Accordingly, a gate channel length is slightly increased on the sidewall 51 of the trench in such a manner that it is not increased on the region along the overall width of the gate channel. Thus, an operation of several electrons entrapped in a barrier liner can be reduced without influence to reaction to an MOSFET device performance.

公开(公告)号：AT420439T

公开(公告)日：2009-01-15

申请号：AT04741612

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14

公开(公告)号：GB2497200B

公开(公告)日：2014-02-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

公开(公告)号：DE69807621D1

公开(公告)日：2002-10-10

申请号：DE69807621

申请日：1998-06-26

Applicant: SIEMENS AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.

公开(公告)号：GB2497200A

公开(公告)日：2013-06-05

申请号：GB201221408

申请日：2012-11-28

Applicant: IBM

Inventor： ZHANG YANLI ,  WANG GENG ,  MESSENGER BRIAN ,  PEI CHENGWEN ,  PARRIES PAUL

IPC: H01L27/108 ,  H01L23/48 ,  H01L23/498

Abstract: A method of forming a trench structure that includes forming a metal containing layer 20 on at least the sidewalls of a trench 10, and forming an undoped semiconductor fill material 25 in the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a second depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a first depth within the trench that is greater than a second depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill 35, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer. In one embodiment a dielectric layer 15 is deposited before the metal contacting layer, the dielectric layer is also recessed. The trench may be formed in a semiconductor 4 on insulator 3 (SOI) structure placed on a base semiconductor 2 where the second depth is within the insulator layer and the first depth is within the base layer. The trench structure may be a capacitor in a memory device with the sidewalls and base of the trench forming the first electrode and the metal containing layer forming the second electrode, an access transistor may be included. In another embodiment the trench structure is a substrate through substrate via structure where the base is planarized to expose the undoped fill material, the metal layer and the dielectric layer, an electrical structure is then bonded to the metallic structure.

公开(公告)号：DE602004018924D1

公开(公告)日：2009-02-26

申请号：DE602004018924

申请日：2004-05-19

Applicant: IBM

Inventor： HANSON DAVID ,  FREDEMAN GREGORY ,  GOLZ JOHN ,  KIM HOKI ,  PARRIES PAUL

IPC: G11C8/08 ,  G11C5/14

公开(公告)号：DE69807621T2

公开(公告)日：2003-11-27

申请号：DE69807621

申请日：1998-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： LEVY MAX G ,  FIEGL BERNHARD ,  BERGNER WOLFGANG ,  GOTH GEORGE R ,  PARRIES PAUL ,  SENDELBACH MATTHEW J ,  WANG TING-HAO ,  WILLE WILLIAM C ,  WITTMANN JUERGEN

IPC: H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/321

Abstract: A method for preventing CMP-induced (chemical-mechanical polish) damage to a substrate disposed below a pad nitride layer of a mesa. The pad nitride layer is disposed below a conformally deposited dielectric layer. The dielectric layer is disposed below a conformally deposited polysilicon layer. The method includes planarizing the polysilicon layer down to at least a surface of the dielectric layer using the CMP to expose a first region of the dielectric layer. The method further includes etching partially through the first region of the dielectric layer using first etch parameters. The first etch parameters include an etchant source gas that is substantially selective to the pad nitride layer to prevent the pad nitride layer from being etched through even in the presence of a CMP defect. Additionally, there is also included removing the polysilicon layer after the etching partially through the first region of the dielectric layer.