公开(公告)号：DE69220452D1

公开(公告)日：1997-07-24

申请号：DE69220452

申请日：1992-10-09

Applicant: IBM

Inventor： KRAMER KEVIN G ,  GAUDENZI GENE J ,  LOUIE TIMOTHY J ,  CROMER DARYL C ,  KING PAUL C

IPC: G06F11/10 ,  G06F12/16 ,  G06F13/36

Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.