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公开(公告)号：DE69908245D1
公开(公告)日：2003-07-03
申请号：DE69908245
申请日：1999-06-24
Applicant: IBM
Inventor： CROMER DARYL C , LOCKER HOWARD , WARD JAMES P , STEINMETZ MICHAEL J
Abstract: A system for monitoring tamper events in a computer system 10 is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means 140 which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer 178 for indicating the time of a tamper event and a management device 160 for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet 200 which includes the time of the tamper event to a system administrator of the network. Preferably the computer system has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system also sends network alerts when the cover is removed.
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公开(公告)号：CA2050950A1
公开(公告)日：1992-04-02
申请号：CA2050950
申请日：1991-09-11
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , CROMER DARYL C , STUTES RODGER M
Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.
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公开(公告)号：DE69220452D1
公开(公告)日：1997-07-24
申请号：DE69220452
申请日：1992-10-09
Applicant: IBM
Inventor： KRAMER KEVIN G , GAUDENZI GENE J , LOUIE TIMOTHY J , CROMER DARYL C , KING PAUL C
Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.
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公开(公告)号：BR9104142A
公开(公告)日：1992-06-02
申请号：BR9104142
申请日：1991-09-26
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , CROMER DARYL C , STUTES ROGER M
Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.
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公开(公告)号：DE69908245T2
公开(公告)日：2004-04-08
申请号：DE69908245
申请日：1999-06-24
Applicant: IBM
Inventor： CROMER DARYL C , LOCKER HOWARD , WARD JAMES P , STEINMETZ MICHAEL J
Abstract: A system for monitoring tamper events in a computer system 10 is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means 140 which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer 178 for indicating the time of a tamper event and a management device 160 for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet 200 which includes the time of the tamper event to a system administrator of the network. Preferably the computer system has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system also sends network alerts when the cover is removed.
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Patent Agency Ranking
公开(公告)号：CA2271534A1
公开(公告)日：2000-01-01
申请号：CA2271534
申请日：1999-05-12
Applicant: IBM
Inventor： CROMER DARYL C , LOCKER HOWARD , WARD JAMES P , STEINMETZ MICHAEL J
Abstract: A system for monitoring tamper events in a computer system is disclosed. The computer system is on a network. The system comprises a tamper realtime clock (RTC) means which receives at least one tamper event signal from the computer system. The tamper RTC includes a timer for indicating the time of a tamper event and a management device for receiving the at least one tamper event signal. The management device issues a command to the tamper RTC means to obtain the time of the at least one tamper event. The management device also generates a network packet which includes the time of the tamper event to a system administrator of the network. The present invention in a preferred embodiment is directed to a computer system which has the ability to functionally detect and store the time of a tamper event. A tamper real time clock (RTC) circuit is operatively connected with logic to store the date and time of an event as it occurs. In a preferred embodiment, the tamper event could be as simple as a toggle switch being activated when a cover on the computer system is removed. The computer system could also send network alerts when the cover is removed.
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公开(公告)号：CA2051175C
公开(公告)日：1998-03-31
申请号：CA2051175
申请日：1991-09-11
Applicant: IBM
Inventor： STUTES RODGER M , BLAND PATRICK M , CROMER DARYL C , ALDEREGUIA ALFREDO
IPC: G11C11/401 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/42 , G11C11/407 , G06F13/16
Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.
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公开(公告)号：CA2050950C
公开(公告)日：1996-01-02
申请号：CA2050950
申请日：1991-09-11
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , CROMER DARYL C , STUTES RODGER M
Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.
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公开(公告)号：BR9103873A
公开(公告)日：1992-06-16
申请号：BR9103873
申请日：1991-09-09
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , BLAND PATRICK M , CROMER DARYL C , STUTES ROGER M
IPC: G11C11/401 , G06F12/00 , G06F12/02 , G06F12/06 , G06F13/42 , G11C11/407 , G06F15/20
Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.
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公开(公告)号：BR9204925A
公开(公告)日：1993-07-06
申请号：BR9204925
申请日：1992-12-08
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , CROMER DARYL C , SENDLEIN KIMBERLY K
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