BIDIRECTIONAL PARALLEL PRINTER INTERFACE

    公开(公告)号:JPH07168678A

    公开(公告)日:1995-07-04

    申请号:JP5939592

    申请日:1992-02-13

    Applicant: IBM

    Abstract: PURPOSE: To make an operator confirm the state of a printer without going to the place of the printer by making a data processor report whether information transmitted to the printer is data signals or state signals. CONSTITUTION: A computer 40 which is the data processor is connected to the printer 41 by a cable 42. When the power of the computer 40 and the printer 41 is turned ON, it is assumed that they are operated in a mode where the printer 41 is placed in a single direction. In order to activate a bidirectional mode so as to make the printer 41 able to transmit and receive the information, the computer 41 sets-INIT to low and the printer 41 sets +BUSY to high in response to it. When the printer 41 is prepared to receive a state command, +BUSY is turned low. In the case that the printer 41 does not set +BUSY, it is assumed that the computer 40 can not respond whether the printer 41 is unidiretional or bidirectional due to the fault of a hardware.

    2.
    发明专利
    未知

    公开(公告)号:DE69229079D1

    公开(公告)日:1999-06-10

    申请号:DE69229079

    申请日:1992-02-26

    Applicant: IBM

    Abstract: A parallel interface connects a data processor and a printer so that each may transmit information to the other or receive information from the other. The transmitted information from the data processor can be data or status signals. The data or status signals are transmitted over the same eight information lines between the data processor and the printer with a predetermined signal being sent over another line from the data processor to the printer prior to transmission over the eight lines to identify whether the transmitted information is data or status signals. The printer sends status signals to the data processor over the same eight information lines after sending a predetermined signal to the data processor over a further line that it is going to transmit.

    3.
    发明专利
    未知

    公开(公告)号:DE69220452D1

    公开(公告)日:1997-07-24

    申请号:DE69220452

    申请日:1992-10-09

    Applicant: IBM

    Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

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