公开(公告)号：EP1497733A4

公开(公告)日：2008-04-30

申请号：EP03728351

申请日：2003-04-07

Applicant: IBM

Inventor： JI BRIAN L ,  HWANG CHORNG-LII ,  KIRIHATA TOSHIAKI K ,  MUNETOH SEIJI

IPC: G06F12/00 ,  G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093 ,  G06F13/00

CPC classification number: G11C8/12 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/3042 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4093 ,  G11C2207/2245

Abstract: A memory storage system (10) is disclosed. In an exemplary embodiment, the memory storage system includes a plurality of memory storage banks (12) and a cache (14) in communication therewith. Both the plurality of memory storage banks (12) and the cache (14) further include destructive read memory storage elements.

公开(公告)号：JP2004087100A

公开(公告)日：2004-03-18

申请号：JP2003275677

申请日：2003-07-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LOUIS RUUCHEN SHEW ,  FREDEMAN GREGORY ,  HWANG CHORNG-LII ,  KIRIHATA TOSHIAKI K ,  PONTIUS DALE E

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC classification number: G11C29/846 ,  G11C2207/104

Abstract: PROBLEM TO BE SOLVED: To provide an effective column restoration system which replaces a defective column element with a redundant element.
SOLUTION: A column redundant device 10 includes a fuse information storage device for every individual microcell to store fuse information indicating the location of any one of defective elements. A first bank address decoding mechanism decodes a reading bank address corresponding to a first microcell and a second bank address decoding mechanism decodes a writing bank address corresponding to a second microcell. When at least one defective column element is included in the first microcell, the device 10 generates an internal column address corresponding to at least one defective column element in the first microcell. Similarly, the device 10 generates an internal column address corresponding to at least one defective column element in the second microcell when at least one defective column element is included in the second microcell.
COPYRIGHT: (C)2004,JPO

公开(公告)号：AU2003234695A1

公开(公告)日：2003-11-10

申请号：AU2003234695

申请日：2003-04-07

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI K ,  MUNETOH SEIJI ,  JI BRIAN L ,  HWANG CHORNG-LII

IPC: G06F12/00 ,  G06F12/08 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093 ,  G06F13/00

Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.

公开(公告)号：AT513264T

公开(公告)日：2011-07-15

申请号：AT03728351

申请日：2003-04-07

Applicant: IBM

Inventor： JI BRIAN L ,  HWANG CHORNG-LII ,  KIRIHATA TOSHIAKI K ,  MUNETOH SEIJI

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/4093

Abstract: A memory storage system includes a plurality of memory storage banks and a cache in communication therewith. Both the plurality of memory storage banks and the cache further include destructive read memory storage elements configured for delayed write back scheduling thereto.