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    System and method for performing selective row energization based on write data
    1.
    发明专利
    System and method for performing selective row energization based on write data 有权
    基于写入数据执行选择性能量的系统和方法

    公开(公告)号：JP2007200523A

    公开(公告)日：2007-08-09

    申请号：JP2006346800

    申请日：2006-12-22

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： LEE MICHAEL JU HYEOK ,  KLIM PETER J ,  JOSE A PAREDES ,  CHU SAM GAT-SHANG

    IPC: G11C11/413 ,  G11C11/407 ,  G11C11/41

    CPC classification number: G11C8/10

    Abstract: PROBLEM TO BE SOLVED: To provide a system and method for performing selective row energization based on write data by using a selective row energization system.
    SOLUTION: The system includes: a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detection circuit 110 which responds to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detection register 112 having M uniform-detection latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated row; and an M-bit row driver device 116 which responds to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种通过使用选择行通电系统来基于写入数据执行选择性行激励的系统和方法。 解决方案：该系统包括：具有M行104和N列106的存储阵列102; N位数据字寄存器108; 均匀检测电路110，响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112，每个均衡检测锁存器114与M行104中的一个相关联并且存储用于存储在相关行中的数据字的统一字数据位; 以及M位行驱动器设备116，其响应M行104中的每一个的均匀字数据位，以禁止均匀字数据位为第一值的M行104的通电。 版权所有（C）2007，JPO＆INPIT

    3.
    发明专利
    未知

    公开(公告)号：BR9202159A

    公开(公告)日：1993-02-02

    申请号：BR9202159

    申请日：1992-06-05

    Applicant: IBM

    Inventor： KLIM PETER J

    IPC: G06F11/10 ,  G06F13/00 ,  H04L1/00

    Abstract: An improved I/O channel check and parity check detector includes two similar detection paths each of which includes a check detector, a glitch reject circuit, and a read back register. A memory parity error causes a bit to be set in the read back register. An I/O channel check sets another bit in a read back register provided a memory parity error has not been signalled. If such signal occurs, the channel check is rejected. The read back bits are read through a port allowing the system to determine the source of error.

    4.
    发明专利
    未知

    公开(公告)号：BR9005533A

    公开(公告)日：1991-09-17

    申请号：BR9005533

    申请日：1990-10-31

    Applicant: IBM

    Inventor： LYFORD AVERY M ,  MOELLER DENNIS L ,  KLIM PETER J

    IPC: G06F9/48 ,  G06F13/24 ,  G06F13/26 ,  G06F9/46

    Abstract: A programmable interrupt controller (8) having a plurality of interrupt request inquest inputs (42, 56)and an interrupt request output (58) for connection to a central processing unit (4) (CPU) includes means for interrupting the CPU (4) over the interrupt request output (58) responsive to an interrupt request from any one of the interrupt request inputs (42, 56) and a priority resolver (92) for assigning a priority position to each of the interrupt request inputs (42, 56) to create an interrupt priority hierarchy. The interrupt controller (8) is programmable such that each interrupt request input may be independently established as responsive to either edge-triggered or level-triggered interrupt requests on a per interrupt basis. An initialization command word register (94) of the interrupt controller has a bit corresponding to each of the interrupt request inputs. Programming each of the bits of the register (94) to one of two states determines whether corresponding interrupt request inputs are edge-sensitive or level-sensitive.

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